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MGX: near-zero overhead memory protection for data-intensive accelerators

Published: 11 June 2022 Publication History

Abstract

This paper introduces MGX, a near-zero overhead memory protection scheme for hardware accelerators. MGX minimizes the performance overhead of off-chip memory encryption and integrity verification by exploiting the application-specific properties of the accelerator execution. In particular, accelerators tend to explicitly manage data movement between on-chip and off-chip memories. Therefore, the general memory access pattern of an accelerator can largely be determined for a given application. Exploiting these characteristics, MGX generates version numbers used in memory encryption and integrity verification using on-chip accelerator state rather than storing them in the off-chip memory; it also customizes the granularity of the memory protection to match the granularity used by the accelerator. To demonstrate the efficacy of MGX, we present an in-depth study of MGX for DNN and graph algorithms. Experimental results show that on average, MGX lowers the performance overhead of memory protection from 28% and 33% to 4% and 5% for DNN and graph processing accelerators in a wide range of benchmarks, respectively.

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  1. MGX: near-zero overhead memory protection for data-intensive accelerators

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      cover image ACM Conferences
      ISCA '22: Proceedings of the 49th Annual International Symposium on Computer Architecture
      June 2022
      1097 pages
      ISBN:9781450386104
      DOI:10.1145/3470496
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 11 June 2022

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      Author Tags

      1. graph algorithms
      2. neural networks
      3. off-chip memory protection
      4. secure accelerators
      5. version number generation

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      ISCA '22 Paper Acceptance Rate 67 of 400 submissions, 17%;
      Overall Acceptance Rate 543 of 3,203 submissions, 17%

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      • (2024)GPU-based Private Information Retrieval for On-Device Machine Learning InferenceProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624855(197-214)Online publication date: 27-Apr-2024
      • (2024)sNPU: Trusted Execution Environments on Integrated NPUs2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00057(708-723)Online publication date: 29-Jun-2024
      • (2024)MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA59077.2024.00056(693-707)Online publication date: 29-Jun-2024
      • (2024)Supporting Secure Multi-GPU Computing with Dynamic and Batched Metadata Management2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00025(204-217)Online publication date: 2-Mar-2024
      • (2023)Triton: Software-Defined Threat Model for Secure Multi-Tenant ML Inference AcceleratorsProceedings of the 12th International Workshop on Hardware and Architectural Support for Security and Privacy10.1145/3623652.3623672(19-28)Online publication date: 29-Oct-2023
      • (2023)SecureLoop: Design Space Exploration of Secure DNN AcceleratorsProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614273(194-208)Online publication date: 28-Oct-2023
      • (2023)Plutus: Bandwidth-Efficient Memory Security for GPUs2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071100(543-555)Online publication date: Feb-2023
      • (2022)Tunable Memory Protection for Secure Neural Processing Units2022 IEEE 40th International Conference on Computer Design (ICCD)10.1109/ICCD56317.2022.00025(105-108)Online publication date: Oct-2022

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