research-article

Simultaneous Placement and Clock Tree Construction for Modern FPGAs

Authors:

Mehrdad E. Dehkordi,

David Z. PanAuthors Info & Claims

FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 132 - 141

https://doi.org/10.1145/3289602.3293897

Published: 20 February 2019 Publication History

Abstract

Modern field-programmable gate array (FPGA) devices often contain complex clocking architectures to achieve high-performance and flexible clock networks. The physical structure of these clock networks, however, are pre-manufactured, unadjustable, and with only limited routing resources. Most conventional FPGA placement algorithms rarely consider clock feasibility, and therefore lead to clock routing failures. Some recent works adopt simplified clock routing models (e.g., the bounding box model) to force clock legality during placement, which, however, can often overestimate clock routing demands and results in unnecessary placement quality degradation. To address these limitations, in this paper, we propose a generic FPGA placement framework that can simultaneously optimize placement quality and ensure clock feasibility by explicit clock tree construction. We demonstrate the effectiveness and efficiency of the proposed approach using the ISPD 2017 Clock-Aware Placement Contest benchmark suite. Compared with other state-of-the-art clock legalization algorithms, the proposed approach can achieve the best routed wirelength with competitive runtime.

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Cited By

Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Zhu ZMei YDeng KHe HChen JYang JChang Y(2024)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329774
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
Show More Cited By

Index Terms

Simultaneous Placement and Clock Tree Construction for Modern FPGAs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Clock-network synthesis
      2. Placement

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Information & Contributors

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Published In

cover image ACM Conferences

FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2019

360 pages

ISBN:9781450361378

DOI:10.1145/3289602

General Chair:
Kia Bazargan
Univ. of Minnesota, USA
,
Program Chair:
Stephen Neuendorffer
Xilinx, USA

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

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Published: 20 February 2019

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FPGA '19

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SIGDA

FPGA '19: The 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 24 - 26, 2019

CA, Seaside, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Di ZTao RMai JChen LLin Y(2024)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line MinimizationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2023.334055471:3(1259-1272)Online publication date: Mar-2024
https://doi.org/10.1109/TCSI.2023.3340554
Zhu ZMei YDeng KHe HChen JYang JChang Y(2024)High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332977443:3(956-969)Online publication date: Mar-2024
https://doi.org/10.1109/TCAD.2023.3329774
Mai JWang JDi ZLin Y(2024)Multielectrostatic FPGA Placement Considering SLICEL–SLICEM Heterogeneity, Clock Feasibility, and Timing OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.331310143:2(641-653)Online publication date: Feb-2024
https://doi.org/10.1109/TCAD.2023.3313101
Kariotis KDadaliaris AKranas GDimitriou GDossis M(2024)Current Status of Analytical FPGA Placement2024 9th South-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference (SEEDA-CECNSM)10.1109/SEEDA-CECNSM63478.2024.00015(30-35)Online publication date: 20-Sep-2024
https://doi.org/10.1109/SEEDA-CECNSM63478.2024.00015
Mai JWang JChen YGuo ZJiang XLiang YLin Y(2024)OpenPARF 3.0: Robust Multi-Electrostatics Based FPGA Macro Placement Considering Cascaded Macros Groups and Fence Regions2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617535(374-379)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10617535
Zapletina MGavrilov S(2023)Pathfinder Algorithm Modification for FPGA Routing StageRussian Microelectronics10.1134/S106373972207012551:7(573-578)Online publication date: 9-Jan-2023
https://doi.org/10.1134/S1063739722070125
Mai JWang JDi ZLuo GLiang YLin Y(2023)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit2023 IEEE 15th International Conference on ASIC (ASICON)10.1109/ASICON58565.2023.10396248(1-4)Online publication date: 24-Oct-2023
https://doi.org/10.1109/ASICON58565.2023.10396248
Beheshti-Shirazi SNazari NGubbi KLatibari BRafatirad SHomayoun HSasan AManoj P(2023)Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop MinimizationIEEE Access10.1109/ACCESS.2023.330453411(87869-87886)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3304534
Zhu ZMei YLi ZLin JChen JYang JChang YOshana R(2022)High-performance placement for large-scale heterogeneous FPGAs with clock constraintsProceedings of the 59th ACM/IEEE Design Automation Conference10.1145/3489517.3530567(643-648)Online publication date: 10-Jul-2022
https://dl.acm.org/doi/10.1145/3489517.3530567
Zapletina MZheleznikov DGavrilov S(2021)Improving Pathfinder Algorithm Perfomance for FPGA Routing2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus51938.2021.9396608(2054-2057)Online publication date: 26-Jan-2021
https://doi.org/10.1109/ElConRus51938.2021.9396608
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