Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/2967938.2967953acmconferencesArticle/Chapter ViewAbstractPublication PagespactConference Proceedingsconference-collections
research-article

Energy Aware Persistence: Reducing Energy Overheads of Memory-based Persistence in NVMs

Published: 11 September 2016 Publication History

Abstract

Next generation byte addressable nonvolatile memories (NVMs) such as PCM, Memristor, and 3D X-Point are attractive solutions for mobile and other end-user devices, as they offer memory scalability as well as fast persistent storage. However, NVM's limitations of slow writes and high write energy are magnified for applications that require atomic, consistent, isolated and durable (ACID) persistence. For maintaining ACID persistence guarantees, applications not only need to do extra writes to NVM but also need to execute a significant number of additional CPU instructions for performing NVM writes in a transactional manner. Our analysis shows that maintaining persistence with ACID guarantees increases CPU energy up to 7.3x and NVM energy up to 5.1x compared to a baseline with no ACID guarantees. For computing platforms such as mobile devices, where energy consumption is a critical factor, it is important that the energy cost of persistence is reduced.
To address the energy overheads of persistence with ACID guarantees, we develop novel energy-aware persistence (EAP) principles that identify data durability (logging) as the dominant factor in energy increase. Next, for low energy states, we formulate energy efficient durability techniques that include a mechanism to switch between performance and energy efficient logging modes, support for NVM group commit, and a memory management method that reduces energy by trading capacity via less frequent garbage collection. For critical energy states, we propose a relaxed durability mechanism -- ACI-RD -- that relaxes data logging without affecting the correctness of an application. Finally, we evaluate EAP's principles with real applications and benchmarks. Our experimental results demonstrate up to 2x reduction in CPU and 2.4x reduction in NVM energy usage compared to the traditional ACID persistence.

References

[1]
Intel-Micron Memory 3D XPoint. http://intel.ly/1eICR0a.
[2]
Intel RAPL driver. http://lwn.net/Articles/545745/.
[3]
JPEG library. http://libjpeg.sourceforge.net/.
[4]
SNIA specification. http://tinyurl.com/nktmrby.
[5]
SQLite. http://www.sqlite.org.
[6]
J. Arulraj, A. Pavlo, and S. R. Dulloor. Let's talk about storage & recovery methods for non-volatile memory database systems. In Proceedings of the 2015 ACM SIGMOD International Conference on Management of Data, SIGMOD '15, pages 707--722, New York, NY, USA, 2015. ACM.
[7]
H. Avni, E. Levy, and A. Mendelson. Hardware Transactions in Nonvolatile Memory, pages 617--630. Springer Berlin Heidelberg, Berlin, Heidelberg, 2015.
[8]
A. M. Caulfield, A. De, J. Coburn, T. I. Mollow, R. K. Gupta, and S. Swanson. Moneta: A high-performance storage array architecture for next-generation, non-volatile memories. In MICRO 2010, pages 385--395.
[9]
D. R. Chakrabarti, H.-J. Boehm, and K. Bhandari. Atlas: Leveraging locks for non-volatile memory consistency. In Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA '14, pages 433--452, New York, NY, USA, 2014. ACM.
[10]
J. Coburn, T. Bunker, M. Schwarz, R. Gupta, and S. Swanson. From aries to mars: Transaction support for next-generation, solid-state drives. In SOSP 2013, pages 197--212.
[11]
J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. Nv-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. In ASPLOS, 2011, pages 105--118.
[12]
J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better i/o through byte-addressable, persistent memory. In SOSP, 2009, pages 133--146.
[13]
I. Constandache, S. Gaonkar, M. Sayler, R. Choudhury, and L. Cox. Enloc: Energy-efficient localization for mobile phones. In INFOCOM 2009, pages 2716--2720, 2009.
[14]
S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. System software for persistent memory. In EUROSYS, 2014, pages 15:1--15:15.
[15]
Google. LevelDb. http://leveldb.org/.
[16]
Google. Snappy Compession. http://tinyurl.com/ku899co.
[17]
R. Hagmann. Reimplementing the cedar file system using logging and group commit. In Proceedings of the Eleventh ACM Symposium on Operating Systems Principles, SOSP '87, pages 155--162, New York, NY, USA, 1987. ACM.
[18]
M. Hähnel, B. Döbel, M. Völp, and H. Härtig. Measuring energy consumption for short code paths using rapl. SIGMETRICS Perform. Eval. Rev., 40(3):13--17, Jan. 2012.
[19]
M. Hertz and E. D. Berger. Quantifying the performance of garbage collection vs. explicit memory management. In OOPSLA, 2015, pages 313--326.
[20]
Intel. Intel Development Manual. http://intel.ly/1CdHj1r.
[21]
Intel. Logging library. https://github.com/pmem/nvml.
[22]
Intel. PMFS: Persistent memory file system. github.com/linux-pmfs.
[23]
S. Kannan, A. Gavrilovska, and K. Schwan. Reducing the cost of persistence for nonvolatile heaps in end user devices. In HPCA, 2014, pages 512--523.
[24]
S. Kannan, A. Gavrilovska, and K. Schwan. pvm: Persistent virtual memory for efficient capacity scaling and object storage. In Proceedings of the Eleventh European Conference on Computer Systems, EuroSys '16, pages 13:1--13:16, New York, NY, USA, 2016. ACM.
[25]
S. Kannan, A. Gavrilovska, K. Schwan, and S. Kumar. Nvm heaps for accelerating browser-based applications. In Proceedings of the 1st Workshop on Interactions of NVM/FLASH with Operating Systems and Workloads, INFLOW '13, pages 8:1--8:8, New York, NY, USA, 2013. ACM.
[26]
S. Kannan, A. Gavrilovska, K. Schwan, and D. Milojicic. Optimizing checkpoints using nvm as virtual memory. In Parallel Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on, pages 29--40, May 2013.
[27]
H. Kim, M. Ryu, and U. Ramachandran. What is a good buffer cache replacement scheme for mobile flash storage? SIGMETRICS Perform. Eval. Rev., 40(1):235--246, June 2012.
[28]
B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In ISCA, 2009, pages 2--13.
[29]
R.-S. Liu, D.-Y. Shen, C.-L. Yang, S.-C. Yu, and C.-Y. M. Wang. Nvm duet: Unified working memory and persistent store architecture. In ASPLOS, 2014, pages 455--470.
[30]
Y. Lu, J. Shu, L. Sun, and O. Mutlu. Loose-ordering consistency for persistent memory. In ICCD, 2014, pages 216--223.
[31]
I. Moraru, D. G. Andersen, M. Kaminsky, N. Tolia, P. Ranganathan, and N. Binkert. Consistent, durable, and safe memory management for byte-addressable non volatile main memory. In Proceedings of the First ACM SIGOPS Conference on Timely Results in Operating Systems, TRIOS '13, pages 1:1--1:17, New York, NY, USA, 2013. ACM.
[32]
D. Narayanan and O. Hodson. Whole-system persistence. In ASPLOS, 2012, pages 401--410.
[33]
G. Oh, S. Kim, S. Lee, and B. Moon. Sqlite optimization with phase change memory for mobile applications. PVLDB, 8(12):1454--1465, 2015.
[34]
K. Paul and T. K. Kundu. Android on mobile devices: An energy perspective. In CIT 2010, pages 2421--2426.
[35]
S. Pelley, P. M. Chen, and T. F. Wenisch. Memory persistency. In ISCA, 2014, pages 265--276.
[36]
S. Pelley, T. F. Wenisch, B. T. Gold, and B. Bridge. Storage management in the nvram era. Proc. VLDB Endow., 7(2):121--132, Oct. 2013.
[37]
M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. SIGARCH Comput. Archit. News, 37(3):24--33, June 2009.
[38]
D. Schwalb, T. Berning, M. Faust, M. Dreseler, and H. Plattner. nvm malloc: Memory allocation for nvram. In VLDB, 2015.
[39]
H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Lightweight persistent memory. In ASPLOS, 2011, pages 91--104.
[40]
C. Wang, S. S. Vazhkudai, X. Ma, F. Meng, Y. Kim, and C. Engelmann. Nvmalloc: Exposing an aggregate ssd store as a memory partition in extreme-scale machines. In Parallel Distributed Processing Symposium (IPDPS), 2012 IEEE 26th International, pages 957--968, May 2012.
[41]
H. Yoon. Row buffer locality aware caching policies for hybrid memories. In ICCD, 2012, pages 337--344.
[42]
J. Zhao, S. Li, D. H. Yoon, Y. Xie, and N. P. Jouppi. Kiln: Closing the performance gap between systems with and without persistence support. MICRO-46, pages 421--432, 2013.
[43]
J. Zhao, O. Mutlu, and Y. Xie. Firm: Fair and high-performance memory control for persistent memory systems. In MICRO-47, 2014, pages 153--165.

Cited By

View all
  • (2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
  • (2023)Back to the Core-Memory Age: Running Operating Systems in NVRAM onlyArchitecture of Computing Systems10.1007/978-3-031-42785-5_11(153-167)Online publication date: 26-Aug-2023
  • (2021)Gengar: An RDMA-based Distributed Hybrid Memory Pool2021 IEEE 41st International Conference on Distributed Computing Systems (ICDCS)10.1109/ICDCS51616.2021.00018(92-103)Online publication date: Jul-2021
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation
September 2016
474 pages
ISBN:9781450341219
DOI:10.1145/2967938
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2016

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. acid
  2. end-user device
  3. energy overheads
  4. heap-based persistence
  5. logging
  6. memory-persistence
  7. nvm
  8. storage

Qualifiers

  • Research-article

Funding Sources

  • Intel URO program on software for persistent memories
  • C- FAR one of the six SRC STARnet Centers sponsored by MARCO and DARPA

Conference

PACT '16
Sponsor:
  • IFIP WG 10.3
  • IEEE TCCA
  • SIGARCH
  • IEEE CS TCPP

Acceptance Rates

PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;
Overall Acceptance Rate 121 of 471 submissions, 26%

Upcoming Conference

PACT '24

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)10
  • Downloads (Last 6 weeks)1
Reflects downloads up to 02 Oct 2024

Other Metrics

Citations

Cited By

View all
  • (2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
  • (2023)Back to the Core-Memory Age: Running Operating Systems in NVRAM onlyArchitecture of Computing Systems10.1007/978-3-031-42785-5_11(153-167)Online publication date: 26-Aug-2023
  • (2021)Gengar: An RDMA-based Distributed Hybrid Memory Pool2021 IEEE 41st International Conference on Distributed Computing Systems (ICDCS)10.1109/ICDCS51616.2021.00018(92-103)Online publication date: Jul-2021
  • (2020)Improving phase change memory performance with data content aware accessProceedings of the 2020 ACM SIGPLAN International Symposium on Memory Management10.1145/3381898.3397210(30-47)Online publication date: 16-Jun-2020
  • (2020)Durable Transactional Memory Can Scale with TimestoneProceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3373376.3378483(335-349)Online publication date: 9-Mar-2020
  • (2020)Disperse Access Considered Energy Inefficiency in Intel Optane DC Persistent Memory Servers2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS)10.1109/ICDCS47774.2020.00107(921-931)Online publication date: Nov-2020
  • (2017)UNITYProceedings of the 7th International Workshop on Runtime and Operating Systems for Supercomputers ROSS 201710.1145/3095770.3095776(1-8)Online publication date: 27-Jun-2017

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media