research-article

Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes

Authors:

Shizun Ge,

Zhen Wang,

Pei Luo,

Mark KarpovskyAuthors Info & Claims

HASP '13: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy

Article No.: 5, Pages 1 - 8

https://doi.org/10.1145/2487726.2487731

Published: 23 June 2013 Publication History

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Abstract

Memories used in cryptographic devices are vulnerable to fault injection attacks. To mitigate the danger of these attacks, error control codes are often used in memories to detect maliciously injected faults. Most of codes proposed for memories in cryptographic devices are error detecting codes with small Hamming distances that cannot be used for error correction. While being able to provide sufficient protection against fault injection attacks, these codes cannot provide a satisfactory reliability under the presence of random errors. In this paper we present reliable and secure memory architectures based on two nonlinear error correcting codes. The presented coding technique can be used for detection of fault injection attacks as well as for correction of random errors. The construction and the error correction procedures for the code will be described. The error handling methodology used to distinguish between random errors and maliciously injected faults will be discussed.

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Cited By

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Maiti SSengupta MChowdhury D(2020)Generating nonlinear codes for multi-bit symbol error correction using cellular automataPhysica D: Nonlinear Phenomena10.1016/j.physd.2020.132758(132758)Online publication date: Oct-2020
https://doi.org/10.1016/j.physd.2020.132758
Levina ATaranov SKaplun DBoyvalenkov P(2019)Wavelet Codes and Their Implementation for Protection of NAND Flash Memory2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring)10.1109/PIERS-Spring46901.2019.9017402(3797-3804)Online publication date: Jun-2019
https://doi.org/10.1109/PIERS-Spring46901.2019.9017402
Hasan MRay B(2019)Tolerance of Deep Neural Network Against the Bit Error Rate of NAND Flash Memory2019 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS.2019.8720586(1-4)Online publication date: Mar-2019
https://doi.org/10.1109/IRPS.2019.8720586
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Index Terms

Secure memories resistant to both random errors and fault injection attacks using nonlinear error correction codes
1. Software and its engineering
  1. Software creation and management
    1. Software development techniques
      1. Error handling and recovery

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Information

Published In

HASP '13: Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy

June 2013

77 pages

ISBN:9781450321181

DOI:10.1145/2487726

Conference Chairs:
Ruby Lee
Princeton University
,
Weidong Shi
University of Houston

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 June 2013

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HASP '13

Sponsor:

SIGARCH

HASP '13: The Second Workshop on Hardware and Architectural Support for Security and Privacy

June 23 - 24, 2013

Tel-Aviv, Israel

Acceptance Rates

HASP '13 Paper Acceptance Rate 9 of 13 submissions, 69%;

Overall Acceptance Rate 9 of 13 submissions, 69%

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Cited By

View all

Maiti SSengupta MChowdhury D(2020)Generating nonlinear codes for multi-bit symbol error correction using cellular automataPhysica D: Nonlinear Phenomena10.1016/j.physd.2020.132758(132758)Online publication date: Oct-2020
https://doi.org/10.1016/j.physd.2020.132758
Levina ATaranov SKaplun DBoyvalenkov P(2019)Wavelet Codes and Their Implementation for Protection of NAND Flash Memory2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring)10.1109/PIERS-Spring46901.2019.9017402(3797-3804)Online publication date: Jun-2019
https://doi.org/10.1109/PIERS-Spring46901.2019.9017402
Hasan MRay B(2019)Tolerance of Deep Neural Network Against the Bit Error Rate of NAND Flash Memory2019 IEEE International Reliability Physics Symposium (IRPS)10.1109/IRPS.2019.8720586(1-4)Online publication date: Mar-2019
https://doi.org/10.1109/IRPS.2019.8720586
Bu LKarpovsky MKinsy M(2018)Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codesIET Computers & Digital Techniques10.1049/iet-cdt.2018.5008Online publication date: 5-Nov-2018
https://doi.org/10.1049/iet-cdt.2018.5008
Levina ATaranov SKaplun DKlionskiy DGulvanskii V(2017)AMD codes based on wavelet transform2017 Progress in Electromagnetics Research Symposium - Fall (PIERS - FALL)10.1109/PIERS-FALL.2017.8293564(2534-2539)Online publication date: Nov-2017
https://doi.org/10.1109/PIERS-FALL.2017.8293564
Ng SPaterson M(2016)Disjoint difference families and their applicationsDesigns, Codes and Cryptography10.1007/s10623-015-0149-478:1(103-127)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1007/s10623-015-0149-4
Bu LKarpovsky MWang Z(2015)New byte error correcting codes with simple decoding for reliable cache design2015 IEEE 21st International On-Line Testing Symposium (IOLTS)10.1109/IOLTS.2015.7229859(200-205)Online publication date: Jul-2015
https://doi.org/10.1109/IOLTS.2015.7229859
Neumeier YKeren O(2014)A new efficiency criterion for security oriented error correcting codes2014 19th IEEE European Test Symposium (ETS)10.1109/ETS.2014.6847800(1-6)Online publication date: May-2014
https://doi.org/10.1109/ETS.2014.6847800

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Statistical properties of side-channel and fault injection attacks using coding theory

Automatic generation of error control codes for computer applications

Faults, Injection Methods, and Fault Attacks