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Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach

Published: 04 December 2011 Publication History

Abstract

Software complexity has increased considerably over recent years, needing special target architectures as MPSoCs to fulfill the heavy memory, communication and computation requirements. Nevertheless, the use of MPSoCs has brought attention to the need for effective methods and tools for parallel software development. Methodologies aggregating partitioning and mapping are normally employed to fulfill the heavy requirements of such systems. This paper explores task-partitioning and processor-mapping methods on homogeneous NoC-Based MPSoC. The effect of both on application's energy consumption is explored alone and jointly. Experiments with several synthetic and four real applications show that the energy consumption is reduced up to 18%, 31.8% or 38.1% when applying partitioning, mapping or both, respectively.

References

[1]
Jalier, C. et al. Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. DATE, pp.184--189, Oct. 2010.
[2]
Le Beux, S. et al. Combining mapping and partitioning exploration for NoC-based embedded systems. JSA, v.56(7), pp.223--232, Jul. 2010.
[3]
Bononi, L. et al. NoC Topologies Exploration based on Mapping and Simulation Models. Digital System Design Architectures, Methods and Tools, 10th Euromicro Conference, pp. 543--546, 29--31 Aug. 2007.
[4]
Leupers, R. and Castrillon, J.; MPSoC programming using the MAPS compiler. ASP-DAC, pp.897--902, 18--21 Jan. 2010.
[5]
Nedjah, N.; Silva, M., V., C. and Mourelle, L., M. Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization. JSA v.57(1), pp. 79--94. Jan. 2011.
[6]
Tsai, K.; Lai, F.; Pan, C.; Xiao, D.; Tan, H. and Lee, H. Design of low latency on-chip communication based on hybrid NoC architecture. NEWCAS Conference, pp.257--260, Jun. 2010.
[7]
Youness, H. et al. A high performance algorithm for scheduling and hardware-software partitioning on MPSoCs, International Conference on Design & Technology of Integrated Systems in Nanoscale Era. pp. 71--76, Apr. 2009.
[8]
Göhringer, D.; Hübner, M.; Benz, M. and Becker, J. A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.259--262, May 2010.
[9]
Liu, T.; Zhao, Y.; Li, M. and Xue, C. J.; Task Assignment with Cache Partitioning and Locking for WCET Minimization on MPSoC. International Conference on Parallel Processing, pp. 573--582, 2010.
[10]
Sherwani, N. A.; Algorithms for VLSI Physical Design Automation, 2nd. Edition. Kluwer Academic Publisher, USA, 1999.
[11]
Zwillinger, D.; Standard Mathematical Tables and Formulae, 30th. Edition. CRC Press Inc., USA, 1996.
[12]
Hu, J. and Marculescu, R. Energy-aware mapping for tile-based NoC architectures under performance constraints. ASP-DAC, pp.233--239, Jan. 2003.
[13]
Murali, S. and De Micheli, G. Bandwidth-constrained mapping of cores onto NoC architectures. DATE, pp. 896--901, Feb. 2004.
[14]
Ye, T.; Benini, L. and De Micheli, G. Analysis of power consumption on switch fabrics in network routers. DAC, pp. 524--529, Jun. 2002.
[15]
Moraes, F et al. HERMES: an infrastructure for low area overhead packet-switching networks on chip. Integration, the VLSI Journal, v.38(1), pp. 69--93, Oct. 2004.
[16]
Marcon, C. et al. CAFES: A framework for intrachip application modeling and communication architecture design. Journal of Parallel and Distributed Computing, v.71(5), pp. 714--728, 2011.
[17]
Kirkpatrick, S.; Gelatt, C. D. and Vecchi, M. P. Optimization by simulated annealing, Science, pp. 671--680, 1983.

Cited By

View all
  • (2017)Leveraging on Deep Memory Hierarchies to Minimize Energy Consumption and Data Access Latency on Single-Chip Cloud ComputersIEEE Transactions on Sustainable Computing10.1109/TSUSC.2017.27066202:2(154-166)Online publication date: 1-Apr-2017
  • (2017)Tree-based algorithm for design space exploration and mapping application onto heterogeneous platforms2017 19th International Symposium on Computer Architecture and Digital Systems (CADS)10.1109/CADS.2017.8310726(1-6)Online publication date: Dec-2017
  • (2014)Pre-mapping Algorithm for Heterogeneous MPSoCsProceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.50(252-257)Online publication date: 5-Jan-2014

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      cover image ACM Other conferences
      NoCArc '11: Proceedings of the 4th International Workshop on Network on Chip Architectures
      December 2011
      69 pages
      ISBN:9781450309479
      DOI:10.1145/2076501
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      New York, NY, United States

      Publication History

      Published: 04 December 2011

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      Author Tags

      1. MPSoC
      2. NoC
      3. mapping
      4. partitioning

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      Overall Acceptance Rate 46 of 122 submissions, 38%

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      View all
      • (2017)Leveraging on Deep Memory Hierarchies to Minimize Energy Consumption and Data Access Latency on Single-Chip Cloud ComputersIEEE Transactions on Sustainable Computing10.1109/TSUSC.2017.27066202:2(154-166)Online publication date: 1-Apr-2017
      • (2017)Tree-based algorithm for design space exploration and mapping application onto heterogeneous platforms2017 19th International Symposium on Computer Architecture and Digital Systems (CADS)10.1109/CADS.2017.8310726(1-6)Online publication date: Dec-2017
      • (2014)Pre-mapping Algorithm for Heterogeneous MPSoCsProceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.50(252-257)Online publication date: 5-Jan-2014

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