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Performance counters and development of SPEC CPU2006

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John L. HenningAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 35, Issue 1

Pages 118 - 121

https://doi.org/10.1145/1241601.1241623

Published: 01 March 2007 Publication History

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Abstract

Performance counters provide the means to track detailed events that occur on a CPU chip. These events are of interest to both performance analysts and compiler developers. Counting them provides essential clues to guide performance improvement. For example, a tester who sees that a program has a high cache miss rate on a particular system may experiment with compilation options that improve prefetching. A compiler developer who sees the same thing may realize that the code generator's machine model is missing some crucial detail of behavior on that particular system.

References

[1]

http://www.spec.org/spec/glossary/#integer

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[2]

http://cooltools.sunsource.net/spot/

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[3]

A. Phansalkar, A. Joshi and L. John, "Subsetting the SPEC CPU2006 Benchmark Suite", Computer Architecture News, vol. 35, no. 1, March 2007.

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[4]

See the two result submissions for the Sun Blade 2000 at www.spec.org/cpu2006/results/res2006q3

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[5]

The manpage for cputrack is available under User Commands at http://docs.sun.com/app/docs/coll/40.10

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[6]

UltraSPARC III Cu User's Manual, Version 2.2.1, January 2004, Chapter 14.

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[7]

J. Henning, SPEC CPU Suite Growth: An Historical Perspective", Computer Architecture News, vol. 35, no. 1, March 2007.

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[8]

R. Weicker and J. Henning, "Subroutine Profiling Results for the CPU2006 Benchmarks", Computer Architecture News, Vol. 35, no. 1, March 2007.

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D. Gove, "CPU2006 Working Set Size", Computer Architecture News, vol. 35, no. 1, March 2007.

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Zhang YFeng DTong WHua YLiu JTan ZWang CWu BLi ZXu G(2018)CACFACM Transactions on Architecture and Code Optimization10.1145/319579915:2(1-26)Online publication date: 23-May-2018
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Performance counters and development of SPEC CPU2006

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 35, Issue 1

March 2007

153 pages

ISSN:0163-5964

DOI:10.1145/1241601

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 March 2007

Published in SIGARCH Volume 35, Issue 1

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Zhang YFeng DTong WHua YLiu JTan ZWang CWu BLi ZXu G(2018)CACFACM Transactions on Architecture and Code Optimization10.1145/319579915:2(1-26)Online publication date: 23-May-2018
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Jamieson PSanaullah AHerbordt M(2018)Benchmarking Heterogeneous HPC Systems Including Reconfigurable Fabrics: Community Aspirations for Ideal Comparisons2018 IEEE High Performance extreme Computing Conference (HPEC)10.1109/HPEC.2018.8547635(1-6)Online publication date: Sep-2018
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Zhang YFeng DLiu JTong WWu BFang C(2017)A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and ReliabilityProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062191(1-6)Online publication date: 18-Jun-2017
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Chen ZXiao NLiu FChen ZChen WXing Y(2016)TBuffer: Constructing a Tail Buffer in DRAM for Flash-Based Main Memory System2016 IEEE 18th International Conference on High Performance Computing and Communications; IEEE 14th International Conference on Smart City; IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC-SmartCity-DSS.2016.0048(276-283)Online publication date: Dec-2016
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Xu CNiu DMuralimanohar NBalasubramonian RZhang TYu SXie Y(2015)Overcoming the challenges of crossbar resistive memory architectures2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2015.7056056(476-488)Online publication date: Feb-2015
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