Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models
Abstract
Cache coherence scalability is a big challenge in shared memory systems. Traditional protocols do not scale due to the storage and traffic overhead of cache invalidation. Tardis, a recently proposed coherence protocol, removes cache invalidation using logical timestamps and achieves excellent scalability. The original Tardis protocol, however, only supports the Sequential Consistency (SC) memory model, limiting its applicability. Tardis also incurs extra network traffic on some benchmarks due to renew messages, and has suboptimal performance when the program uses spinning to communicate between threads. In this paper, we address these downsides of Tardis protocol and make it significantly more practical. Specifically, we discuss the architectural, memory system and protocol changes required in order to implement the TSO consistency model on Tardis, and prove that the modified protocol satisfies TSO. We also describe modifications for Partial Store Order (PSO) and Release Consistency (RC). Finally, we propose optimizations for better leasing policies and to handle program spinning. On a set of benchmarks, optimized Tardis improves on a full-map directory protocol in the metrics of performance, storage and network traffic, while being simpler to implement.
- Publication:
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arXiv e-prints
- Pub Date:
- November 2015
- DOI:
- 10.48550/arXiv.1511.08774
- arXiv:
- arXiv:1511.08774
- Bibcode:
- 2015arXiv151108774Y
- Keywords:
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- Computer Science - Hardware Architecture
- E-Print:
- 14 pages