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Low-Complexity Memory Access Architectures for Quasi-Cyclic LDPC Decoders Ming-Der SHIEH Shih-Hao FANG Shing-Chung TANG Der-Wei YANG Publication IEICE TRANSACTIONS on Information and Systems Vol.E95-D No.2 pp.549-557 Publication Date: 2012/02/01 Online ISSN: 1745-1361 DOI: 10.1587/transinf.E95.D.549 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Computer System Keyword: error control coding, low-density parity-check (LDPC) codes, quasi-cyclic (QC) LDPC codes, partially parallel architecture, VLSI design, Full Text: PDF(752.7KB)>>
Summary: Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders. | ||||||||||
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