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Design of High-Performance CMOS Level Converters Considering PVT Variations Jinn-Shyan WANG Yu-Juey CHANG Chingwei YEH Publication IEICE TRANSACTIONS on Electronics Vol.E94-C No.5 pp.913-916 Publication Date: 2011/05/01 Online ISSN: 1745-1353 DOI: 10.1587/transele.E94.C.913 Print ISSN: 0916-8516 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: level converter, voltage scaling, dual-VDD, PVT variations, Full Text: PDF(897.6KB)>>
Summary: CMOS SoCs can reduce power consumption while maintaining performance by adopting voltage scaling (VS) technologies. The operating speed of the level converter (LC) strongly affects the effectiveness of VS technologies. However, PVT variations can cause serious problems to the LC, because the state-of-the-art LC designs do not give enough attention to this issue. In this work, we proposed to analyze the impact of PVT variations on the performance of the LC using a previously developed heuristic sizing methodology. Based on the evaluation results from different operating corners with different offset voltages and temperatures, we proposed a variation-tolerant LC that achieves both high performance and low energy with a high tolerability for PVT variations. | |||||
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