5.0 mm2 in 0.18 µm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency." />
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A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation

Yoshiki YUNBE
Masayuki MIYAMA
Yoshio MATSUDA

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E93-D    No.12    pp.3284-3293
Publication Date: 2010/12/01
Online ISSN: 1745-1361
DOI: 10.1587/transinf.E93.D.3284
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer System
Keyword: 
affine motion model,  motion estimation,  video segmentation,  real-time processing,  VLSI,  FPGA,  

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Summary: 
This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.05.0 mm2 in 0.18 µm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency.

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