m-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than 3.5% and lower a peaking in the passband filter characteristics. An experimental complex BPF using 0.18 µm CMOS technology can successfully reduce the tuning error from an initial value of -20% to less than 2.5% after tuning. The filter block dimensions are 1.22 mm1.01 mm; and in measurement results of the developed complex BPF with the automatic digital tuning circuit, current consumption is 705 µA and the image rejection ratio is 40.3 dB. Complete evaluation of the BPF indicates that this technique can be applied to low-power, low-cost transceivers." />
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Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers

Hideaki KONDO
Masaru SAWADA
Norio MURAKAMI
Shoichi MASUI

Publication
IEICE TRANSACTIONS on Electronics   Vol.E92-C    No.10    pp.1304-1310
Publication Date: 2009/10/01
Online ISSN: 1745-1353
DOI: 10.1587/transele.E92.C.1304
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Integrated Electronics
Keyword: 
tunable filter,  bandpass filter,  calibration,  radio receiver,  frequency control,  

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Summary: 
This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than 3.5% and lower a peaking in the passband filter characteristics. An experimental complex BPF using 0.18 µm CMOS technology can successfully reduce the tuning error from an initial value of -20% to less than 2.5% after tuning. The filter block dimensions are 1.22 mm1.01 mm; and in measurement results of the developed complex BPF with the automatic digital tuning circuit, current consumption is 705 µA and the image rejection ratio is 40.3 dB. Complete evaluation of the BPF indicates that this technique can be applied to low-power, low-cost transceivers.