Memory controller architectures: A comparative study

K Khalifa, H Fawzy, S El-Ashry… - 2013 8th IEEE Design …, 2013 - ieeexplore.ieee.org
… It is the task of the memory controller to manage these devices. To improve this … The main
aim of the memory controller is to provide the most suitable interface and protocol between the …

Design of memory controller Design of general purpose memory controller

PS Il, SJ Yeol, PS Hwi, JJ Hoon - 2008 International SoC …, 2008 - ieeexplore.ieee.org
The memory controller input gets from information to maneuver memory and a command
signal to external interface from processors. Above picture showed in a command signal to …

A study of performance impact of memory controller features in multi-processor server environment

C Natarajan, B Christenson, F Briggs - … of the 3rd workshop on Memory …, 2004 - dl.acm.org
… more and more important to optimize the memory controller features to obtain the maximum
… can be obtained by carefully optimizing the memory controller features. For instance, one of …

A novel memory controller architecture

K Khalifa, H Fawzy, S El-Ashry… - 2014 11th International …, 2014 - ieeexplore.ieee.org
… It is the task of the memory controller to manage these devices. To … The main aim of the
memory controller is to provide the most suitable interface and protocol between the host and the …

[BOOK][B] Memory controllers for real-time embedded systems

B Akesson, K Goossens - 2011 - Springer
… Inspiration for the memory controller designed in this project … The memory controller proposed
in this book is a hybrid … a hardware implementation of the memory controller integrated in a …

2: Lazy MemCopy at the Memory Controller

AK Kamath, S Peter - 2024 ACM/IEEE 51st Annual …, 2024 - ieeexplore.ieee.org
the memory controller. As all memory accesses are marshaled by the memory controller, we
… We propose performing Memory Copies lazily at the Memory Controller, ie, (MC) 2 . (MC) 2 …

Memory controller optimizations for web servers

S Rixner - … Symposium on Microarchitecture (MICRO-37'04), 2004 - ieeexplore.ieee.org
… Aggressive scheduling within the memory controller to exploit the available parallelism and
locality can reduce the average read latency of the SDRAM. However, bank conflicts and the …

The impulse memory controller

L Zhang, Z Fang, M Parker, BK Mathew… - IEEE Transactions …, 2001 - ieeexplore.ieee.org
… the organization of the memory controller itself, as well as the system call interface that
applications use to control it. The operating system must mediate use of the memory controller to …

A memory controller with an integrated graphics processor

J Watkins, R Roth, M Hsieh, W Radke… - Proceedings of 1993 …, 1993 - ieeexplore.ieee.org
… item comes back from the memory controller. For the SX store instruction, there is never
anything written back to the register file as all the data are sourced to the memory controller to be …

Architecture and analysis of a dynamically-scheduled real-time memory controller

Y Li, B Akesson, K Goossens - Real-Time Systems, 2016 - Springer
… and consider the system bus and the memory controller as a poorly documented black box,
… important part of that black box (the memory controller) and provides results that are required …