An 8 bit 4 gs/s 120 mw cmos adc
H Wei, P Zhang, BD Sahoo… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
<?Pub Dtl=""?>A time-interleaved ADC employs four pipelined time-interleaved channels
along with a new timing mismatch detection algorithm and a high-resolution variable delay line…
along with a new timing mismatch detection algorithm and a high-resolution variable delay line…
A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process
H Jia, X Guo, X Zheng, X Xu, D Wu, L Zhou, J Wu, X Liu - Electronics, 2020 - mdpi.com
This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved
(TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS…
(TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS…
A 4-GS/s Digitally Interpolated 8-Bit Concurrent Binary Search ADC
This letter describes a 4-GS/s four-way time-interleaved binary search analog-to-digital
converter (ADC) in 65-nm CMOS. The ADC improves the conversion speed and resolution by …
converter (ADC) in 65-nm CMOS. The ADC improves the conversion speed and resolution by …
An 8-Gs/s 12-bit TIADC system with real-time broadband mismatch error correction
L Zhao, Z Jiang, R Dong, Z Cao, X Gao… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
High sampling speed can be achieved using multiple analog-to-digital converters (ADCs)
based on the time-interleaved analog-to-digital conversion (TIADC) technique. Various types …
based on the time-interleaved analog-to-digital conversion (TIADC) technique. Various types …
A 14 bit 10MS/s TI SAR ADC with Neural Network Calibration
M Song, X Cao - IEICE Electronics Express, 2025 - jstage.jst.go.jp
In this paper, a four-channel 14bit 10M/S TI SAR ADC with 1.8 V power supply voltage and
1V reference voltage is implemented on the Cadence platform. At the same time, a calibration …
1V reference voltage is implemented on the Cadence platform. At the same time, a calibration …
A 1.6-GS/s 12.2-mW seven-/eight-way split time-interleaved SAR ADC achieving 54.2-dB SNDR with digital background timing mismatch calibration
This article presents a split time-interleaved (TI) successive-approximation register (SAR)
analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It …
analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It …
An 8-bit 10-GHz 21-mW time-interleaved SAR ADC with grouped DAC capacitors and dual-path bootstrapped switch
E Swindlehurst, H Jensen, A Petrie… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
An 8-bit 10-GHz 8 × time-interleaved successive-approximation-register (SAR) analog-to-digital
converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) …
converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) …
A 56-Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16-nm FinFET
Y Frans, J Shin, L Zhou, P Upadhyaya… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
A 56-Gb/s PAM4 wireline transceiver testchip is implemented in 16-nm FinFET. The current
mode logic transmitter incorporates an auxiliary current injection at the output nodes to …
mode logic transmitter incorporates an auxiliary current injection at the output nodes to …
A 7-bit 3.8-GS/s 2-way time-interleaved 4-bit/cycle SAR ADC 16× time-domain interpolation in 28-nm CMOS
D Li, X Zhao, Y Shen, S Liu… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation
register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time …
register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time …
A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture
J Ding, Y Huang, H Zhang, T Feng, F Wang, D Li… - Microelectronics …, 2024 - Elsevier
This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC)
with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The …
with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The …