Circuit enhancement by eliminating long false paths

In this paper, we consider the problem of determining the smallest clock period for a combinational circuit. By considering both the long and short paths, we derive three independent bounds on the clock period. The first bound is the difference between ...

In high level synthesis, resource sharing may result in a circuit containing false loops that pose great difficulty in timing validation during design sign-off phase. It is hence desirable to avoid generating any false loops in a synthesized circuit. ...

Reducing the rate of false positives is of vital importance in enhancing the usefulness of signature-based network intrusion detection systems (NIDSs). To reduce the number of false positives, a network administrator must thoroughly investigate a ...