An adaptive heuristic algorithm for VLSI test vectors selectionWalid Ibrahim, Hesham El-Sayed, Amr El-Chouemie and Hoda Amer European Journal of Operational Research, 2009, vol. 199, issue 3, 630-639 Abstract: The increasing complexity of today's system-on-a-chip designs is putting more pressure on the already stressed design verification process. The verification plan must cover several individual cores as well as the overall chip design. Conditions to be verified are identified by the system's architects, the designers, and the verification team. Testing for these conditions is a must for the design to tape out, especially for high priority conditions. A significant bottleneck in the verification process of such designs is that not enough time is usually given to the final coverage phase, which makes computing cycles very precious. Thus, intelligent selection of test vectors that achieve the best coverage using the minimum number of computing cycles is crucial for on time tape out. This paper presents a novel heuristic algorithm for test vectors selection. The algorithm attempts to achieve the best coverage level while minimizing the required number of computing cycles. Keywords: Heuristic; algorithms; Integer; programming; VLSI; Verification; SCP (search for similar items in EconPapers) Downloads: (external link) Related works: Export reference: BibTeX RIS (EndNote, ProCite, RefMan) HTML/Text Persistent link: https://EconPapers.repec.org/RePEc:eee:ejores:v:199:y:2009:i:3:p:630-639 Access Statistics for this article European Journal of Operational Research is currently edited by Roman Slowinski, Jesus Artalejo, Jean-Charles. Billaut, Robert Dyson and Lorenzo Peccati More articles in European Journal of Operational Research from Elsevier |
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