Cited By
View all- Rahimi KZhou HMacii EYan ZMassoud Y(2007)Minimizing peak power in synchronous logic circuitsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228847(247-252)Online publication date: 11-Mar-2007
Timing Correction and Optimization with Adaptive Delay Sequential Elements
Page 21416
Abstract
This paper introduces Adaptive Delay Sequential Elements (ADSEs). ADSEs are registers that use nonvolatile, floating-gate transistors to tune their internal clock delays. We propose ADSEs for correcting timing violations and optimizing circuit performance. We present an ADSE circuit example, system architecture, and tuning methodology. We present experimental results that demonstrate the correct operation of our example circuit and discuss the die-area impact of using ADSEs. Our experiments also show that voltage and temperature sensitivity ofADSEs are comparable to non-adaptive flip-flops.
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Index Terms
- Timing Correction and Optimization with Adaptive Delay Sequential Elements
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February 2004
606 pages
ISBN:0769520855
Copyright © Copyright (c) 2004 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
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IEEE Computer Society
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Published: 16 February 2004
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Cited By
View all- Rahimi KZhou HMacii EYan ZMassoud Y(2007)Minimizing peak power in synchronous logic circuitsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228847(247-252)Online publication date: 11-Mar-2007
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