Nothing Special   »   [go: up one dir, main page]

skip to main content
10.5555/968879.969176acmconferencesArticle/Chapter ViewAbstractPublication PagesdateConference Proceedingsconference-collections
Article

Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays

Published: 16 February 2004 Publication History

Abstract

Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of time-consuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domain-specific reconfigurable arrays that have demonstrated up to 75% reduction in power consumption when compared to generic FPGA architecture, which makes them suitable for portable devices. This paper presents and compares different configurations of the arrays to efficiently implementing DCT and motion estimation algorithms. A number of algorithms are mapped into the various reconfigurable fabrics demonstrating the flexibility of the new reconfigurable SoC architecture and its ability tosupport a number of implementations having different performance characteristics

References

[1]
{1} Khawam S., Arslan T., Westall F., "Embedded reconfigurable array targeting motion estimation applications", Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, May 2003, Vol. 2, pp. 760-763.
[2]
{2} Khawam S., Arslan T., F. Westall F., "Domain-specific reconfigurable array for Distributed Arithmetic", Proceedings of the 13th International Conference on Field Programmable Logic and Applications, FPL 2003, Sept. 2003, pp. 1139-1144.
[3]
{3} Ahmed N., Natrajan T., Rao K. R., "Discrete Cosine Transform" IEEE Tans. On Computers, Vol. C-23, No. 1, pp. 90- 93, Dec. 1984.
[4]
{4} White, S. A, "Applications of distributed arithmetic to digital signal processing: a tutorial review", ASSP Magazine, IEEE, Volume: 6 Issue: 3, Jul. 1989, Page(s): 4-19.
[5]
{5} Sungwook Yu, Swartzlander, E. E., Jr., "DCT implementation with distributed arithmetic", IEEE transactions on Computers, Vol. 50 Is. 9, Sept. 2001.
[6]
{6} B. G. Lee. "A new algorithm to computer the discrete cosine transform" IEEE Transactions on Accoustics, Speech and Signal Processing, ASSP-32:1243-1245, Dec. 1984.
[7]
{7} P. Pirsch, N. Demassieux and W. Gehrke, "VLSI architectures for video compression-a survey", Proceedings of the IEEE, 83:220-246, Feb. 1995.
[8]
{8} Yi Yang, Chunyan Wang, Omair Ahmed, M., Swamy M. N. S., "An online CORDIC based 2-D IDCT implementation using distributed arithmetic", 6th Inter. Symp. on Signal Processing and its applications,. 2001, Vol. 1.
[9]
{9} Sungwook Yu, Swartzlander, E. E., Jr., "A scaled DCT architecture with the CORDIC algorithm" IEEE Transactions on Signal Processing, Vol. 50, Jan. 2002.
[10]
{10} W. S. Wong, A. Berno, Hussein M. A., "A fast VLSI chip for computing the two-dimensional discrete cosine transform", IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing, 1993., Vol.: 2, pp: 662-665.
[11]
{11} W. Li, "A new algorithm to computer the DCT and its inverse", IEEE Transactions on Signal Processing, Vol. 39 no. 6, pp. 1305-1313, Jun. 1991.
[12]
{12} Komarek, T.; Pirsch, P., Array architectures for block matching algorithms, IEEE Transactions on Circuits and Systems, Vol. 36 Issue: 10, Oct. 1989.
[13]
{13} Yang, K.-M.; Sun, M.-T.; Wu, L., A family of VLSI designs for the motion compensation block-matching algorithm, IEEE Transactions on Circuits and Systems, Vol. 36 Issue: 10, Oct. 1989.
[14]
{14} De Vos, L.; Stegherr, M.; Noll, T. G., VLSI architectures for the full-search blockmatching algorithm, International Conference on Acoustics, Speech, and Signal Processing, 1989. ICASSP-89., 1989.
[15]
{15} Stechele, W., Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs, International Symposium on VLSI Technology, Systems, and Applications, 2001.
[16]
{16} Xiao-Dong Zhang; Chi-Ying Tsui; An efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE.
[17]
{17} Kin-Hung Lam; Chi-Ying Tsui; Low power 2-D array VLSI architecture for block matching motion estimation using computation suspension, Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on, 11-13 Oct. 2000.
[18]
{18} Elgamel, M. A.; Shams, A. M.; Xi Xueling; Bayoumi, M. A.; Enhanced low power motion estimation VLSI architectures for video compression, Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE Inte. Symp. on, Vol.: 4.
[19]
{19} Elgamel, M. A.; Shams, A. M.; Bayoumi, M. A.; A comparative analysis for low power motion estimation VLSI architectures, Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on, 11-13 Oct. 2000.
[20]
{20} Sousa, L.; Roma, N.; Low-power array architectures for motion estimation, Multimedia Signal Processing, 1999 IEEE 3rd Workshop on, 13-15 Sept. 1999.

Cited By

View all
  • (2005)Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless CommunicationProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.173Online publication date: 4-Apr-2005

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2
February 2004
606 pages
ISBN:0769520855

Sponsors

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 February 2004

Check for updates

Qualifiers

  • Article

Conference

DATE04
Sponsor:

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25
Design, Automation and Test in Europe
March 31 - April 2, 2025
Lyon , France

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)1
  • Downloads (Last 6 weeks)0
Reflects downloads up to 13 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2005)Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless CommunicationProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.173Online publication date: 4-Apr-2005

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media