Article

Are Our Design for Testability Features Fault Secure?

Authors:

C. Metra,

T. M. Mak,

M. OmañaAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

Page 10714

Published: 16 February 2004 Publication History

Get Access

Abstract

We analyze the risks associated with faults affecting some common Design For Testability (DFT) features employed within digital products. We will show that some DFT structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the Fault Secure property and we will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults within the DFT structures.

References

[1]

[1] M. Tripp, T. M. Mak, A. Meixner, "Elimination of Traditional Functional Testing of Interface Timings at Intel", to appear in Proc. of Int. Test Conf., 2003.

Digital Library

Google Scholar

[2]

[2] D. D. Josephson, S. Poehlman, and V. Govan, "Debug Methodology for the McKinley Processor", in Proc. of Int. Test Conf., 2001, pp. 451-460.

Digital Library

Google Scholar

[3]

[3] T. Litt, "Support for Debugging in the Alpha 21364 Microprocessor", in Proc. of IEEE Int. Test Conf., 2002, pp. 584-589.

Digital Library

Google Scholar

[4]

[4] J. E. Smith and G. Metze, "Strongly fault-secure logic networks," IEEE Trans. Comput., vol. C-27, pp. 491-499, June 1978.

Google Scholar

[5]

[5] W. C. Carter and P. R. Schneider, "Design of dynamically checked computers," in Proc. IFIP '68, Edinburgh, Scotland, pp. 878-883, 1968.

Google Scholar

[6]

[6] F. Karimi, F. Lombardi, "Parallel Testing of Multi-Port Static Random Access Memories for BIST", in Proc. of The Int. Symp. on Defect and Fault Tolerance in VLSI Systems, 2001.

Digital Library

Google Scholar

[7]

[7] B. Bailey, A. Metayer, B. Svrcek, N. Tendolkar, E: Wolf, E. Fiene, M. Alexander, R. Woltenberg, R. Raina, "Test Methodology for 15's High Performance e500 Core Based on PowerPC Instruction Set Architecture", in Proc. of IEEE Int. Test Conf., 2002, pp. 574-583.

Digital Library

Google Scholar

[8]

[8] Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices", pp. 4-9, 1993.

Google Scholar

[9]

[9] M. Omaña, D. Rossi, C. Metra, "High Speed and Highly Testable Parallel Two-Rail Code Checker", in Proc. of Design, Aut. and Test in Europe Conf., 2003.

Digital Library

Google Scholar

[10]

[10] C. Metra, M. Favalli, B. Riccò, "On-Line Testing Scheme for Clock's Faults", in Proc. of Int. Test Conf., 1997, pp. 587-596.

Digital Library

Google Scholar

Index Terms

Are Our Design for Testability Features Fault Secure?
1. Hardware

Recommendations

Fault secureness need for next generation high performance microprocessor design for testability structures
CF '04: Proceedings of the 1st conference on Computing frontiers

We analyze the risks associated with faults affecting some Design For Testability (DFT) features employed within todays' high performance microprocessors. We will show that, because of the occurrence of internal faults, some of these structures may ...
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a ...
Design for Primitive Delay Fault Testability
ITC '97: Proceedings of the 1997 IEEE International Test Conference

To guarantee the temporal correctness of a digital circuit a set of multiple path delay faults called primitivefaults need to be tested. Primitive faults can contain one or more faulty paths. Existing techniquescan identify and test primitive faults ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

February 2004

688 pages

ISBN:0769520855

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 February 2004

Check for updates

Qualifiers

Article

Conference

DATE04

Sponsor:

SIGDA

DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

0
Total Citations
85
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 21 Nov 2024

Other Metrics

View Author Metrics

Citations

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Index Terms

Recommendations

Fault secureness need for next generation high performance microprocessor design for testability structures

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Design for Primitive Delay Fault Testability