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Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning

Published: 16 February 2004 Publication History

Abstract

In this paper, we propose a combined solution that allows us to customize the architecture of internally partitioned SRAM macros according to the given application be executed. Energy savings with respect to monolithic memory configurations are above 40%, without access time violation.

References

[1]
{1} S. L. Coumeri, D. E. Thomas, "An Environment for Exploring Low-Power Memory Configurations in System-Level Design," ICCD-99, pp. 348-353, Austin, TX, October 1999.
[2]
{2} L. Benini, L. Macchiarulo, A. Macii, M. Poncino, "Layout-Driven Memory Synthesis for Embedded Systems-on-Chip," IEEE TVLSI, Vol. 10, No. 2, pp. 96-105, April 2002.
[3]
{3} A. Karandikar, K. K. Parhii "Low Power SRAM Design using Hierarchical Divided Bit-Line Approach," ICCD-98, pp. 82-88, Austin, TX, October 1998.
[4]
{4} M. Yoshimoto et al. "A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM," IEEE JSSC, Vol. 18, No. 5, pp. 479-485, October 1983.
[5]
{5} P. Shivakumar, N. P. Jouppi, CACTI 3.0: An Integrated Cache Timing, Power and Area Model, WRL Research Report 2001/2, Compaq Western Research Labs, Palo Alto, CA, December 2001.

Cited By

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  • (2005)Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057751(377-380)Online publication date: 17-Apr-2005

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Published In

cover image ACM Conferences
DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1
February 2004
688 pages
ISBN:0769520855

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IEEE Computer Society

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Published: 16 February 2004

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  • (2005)Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMsProceedings of the 15th ACM Great Lakes symposium on VLSI10.1145/1057661.1057751(377-380)Online publication date: 17-Apr-2005

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