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PHIDEO: a silicon compiler for high speed algorithms

Authors:

P. E. R. Lippens,

J. L. van Meerbergen,

O. P. McArdleAuthors Info & Claims

EURO-DAC '91: Proceedings of the conference on European design automation

Pages 436 - 441

Published: 25 February 1991 Publication History

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Abstract

PHIDEO is a silicon compiler targeted at the design of high performance real time systems with high sampling frequencies such as HDTV. It supports the complete design trajectory starting from a high level specification all the way down to layout. New techniques are used to perform global optimisations across loop boundaries in hierarchical flow graphs. The compiler is based on a new target architectural model. Apart from the data-paths special attention is paid to memory optimisation. The new techniques are demonstrated using a progressive scan conversion algorithm.

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Cited By

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Huang CRavi SRaghunathan AJha N(2007)Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90409615:11(1191-1204)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.904096
Gupta SMiranda MCatthoor FGupta RBolsens I(2000)Analysis of high-level address code transformations for programmable processorsProceedings of the conference on Design, automation and test in Europe10.1145/343647.343683(9-13)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.343683
Jemai AKission PJerraya ADewilde PRammig FMusgrave G(1998)Architectural simulation in the context of behavioral synthesisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368303(590-595)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368303
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Information & Contributors

Information

Published In

EURO-DAC '91: Proceedings of the conference on European design automation

February 1991

577 pages

ISBN:0818621303

Conference Chair:
Tony Ambler
Brunel University, Uxbridge, UK
,
General Chair:
Jochen Jess
TU Eindhoven, Eindhoven, The Netherlands
,
Program Chair:
Hugo De Man
KU Leuven/IMEC, Leuven, Belgium

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 25 February 1991

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Cited By

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Huang CRavi SRaghunathan AJha N(2007)Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.90409615:11(1191-1204)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.904096
Gupta SMiranda MCatthoor FGupta RBolsens I(2000)Analysis of high-level address code transformations for programmable processorsProceedings of the conference on Design, automation and test in Europe10.1145/343647.343683(9-13)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.343683
Jemai AKission PJerraya ADewilde PRammig FMusgrave G(1998)Architectural simulation in the context of behavioral synthesisProceedings of the conference on Design, automation and test in Europe10.5555/368058.368303(590-595)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368303
Verhaegh WAarts Evan Gorp PYasuura H(1998)Period assignment in multidimensional periodic schedulingProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289090(585-592)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.289090
Verhaegh WLippens PAarts Evan Meerbergen J(1997)Multidimensional periodic schedulingProceedings of the 1997 European conference on Design and Test10.5555/787260.787706Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787706
Miranda MKaspar MCatthoor Fde Man H(1997)Architectural Exploration and Optimization for Counter Based Hardware Address GenerationProceedings of the 1997 European conference on Design and Test10.5555/787260.787679Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787679
Kienhuis BDeprettere EVissers Kvan der Wolf P(1997)An Approach for Quantitative Analysis of Application-Specific Dataflow ArchitecturesProceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors10.5555/784893.784983Online publication date: 14-Jul-1997
https://dl.acm.org/doi/10.5555/784893.784983
Trainor DWoods RMccanny J(1997)Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS"Journal of VLSI Signal Processing Systems10.5555/255436.281294816:1(41-55)Online publication date: 1-May-1997
https://dl.acm.org/doi/10.5555/255436.2812948
Trainor DWoods RMcCanny J(1997)Architectural Synthesis of Digital Signal ProcessingAlgorithms Using “IRIS”Journal of VLSI Signal Processing Systems10.5555/255436.25544516:1(41-55)Online publication date: 1-May-1997
https://dl.acm.org/doi/10.5555/255436.255445
Miranda MCatthoor FJanssen MHugo de Man (1996)ADOPTProceedings of the 9th international symposium on System synthesis10.5555/524431.857931Online publication date: 6-Nov-1996
https://dl.acm.org/doi/10.5555/524431.857931
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PHIDEO: High-level synthesis for high throughput applications

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