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Micro-computer oriented algorithms for delay evaluation of MOS gates

Authors:

D. Etiemble,

V. Adeline,

Nguyen H. Duyet,

J. C. BallegeerAuthors Info & Claims

DAC '84: Proceedings of the 21st Design Automation Conference

Pages 358 - 364

Published: 25 June 1984 Publication History

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Abstract

We present microcomputer-oriented algorithms to calculate very quickly the switching times and propagation delays of basic CMOS and NMOS gates. The results show less than 10% difference with model 1 SPICE 2-G results.

References

[1]

Ed SEEWANN "Switching Speeds of MOS Inverters" in IEEE J. Solid State Circuits. Vol SC-15 N 2. April 80.

Google Scholar

[2]

Sung Mo KANG "A Design of CMOS Polycells for LSI Circuits" in IEEE Trans. on Circuits and systems. Vol CAS-28 N 8. August 81

Google Scholar

[3]

L. W. Nagel, "SPICE2: A computer program to simulate semiconductor circuits", Electronics Res. Lab. Rep. ERL-M520, Univ. California, Berkeley, May 1975.

Google Scholar

[4]

B. R. Chawla, H.K. Gummel, and P. Kozak, "MOTIS-An MOS timing simulator", IEEE Trans. Circuits Syst., Vol. CAS-22, pp. 901-910, Dec. 1975.

Google Scholar

[5]

Ekachai Lelarasmee, Albert E. Ruehli, and Alberto L. Sangiovanni-Vincentelli, "The waveform relaxation method for time-domain analysis of large scale integrated circuits", IEEE Trans. on Computer-aided design of integr. circuits and systems, Vol. CAD-1, NO. 3, July 1982.

Google Scholar

[6]

H. SHICHMAN and D.A. HODGES "Modeling and Simulation of Insulated Gate Field Effect Transistor Switching Circuits" in IEEE J. of Solid State Circuits. Vol SC-3. September 1968.

Google Scholar

[7]

M. OBREBSKA "Etude comparative de differentes methodes de conception des parties controle des microproesseurs" These de Docteur Ingenieur. Grenoble. June 1982

Google Scholar

[8]

K. BARABAN,M. ISRAEL and J.L. KORS "An interactive Design Rules Checker" in ICCAD-83

Google Scholar

[9]

G. NOGUEZ "Interactive Design Checking Based On Behavior Simulation" in ICCAD-83

Google Scholar

Index Terms

Micro-computer oriented algorithms for delay evaluation of MOS gates
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors
2. Mathematics of computing
  1. Mathematical analysis
    1. Integral equations

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Published In

DAC '84: Proceedings of the 21st Design Automation Conference

June 1984

715 pages

ISBN:0818605421

Publisher

IEEE Press

Publication History

Published: 25 June 1984

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DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Index Terms

Recommendations

Comparison of resonant tunneling currents in double gate MOS diodes with metal and Poly-Silicon gates

Reliability of MOS devices with tungsten gates

Inverter models of CMOS gates for supply current and delay evaluation