A method for IC layout verification
Abstract
A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.
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- A method for IC layout verification
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Published In
June 1984
715 pages
ISBN:0818605421
Sponsors
- SIGDA: ACM Special Interest Group on Design Automation
- IEEE: Institute of Electrical and Electronics Engineers
- IEEE-CS: Computer Society
Publisher
IEEE Press
Publication History
Published: 25 June 1984
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DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%
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