Nothing Special   »   [go: up one dir, main page]

skip to main content
10.5555/800033.800769acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free access

THEMIS logic simulator - a mix mode, multi-level, hierarchical, interactive digital circuit simulator

Published: 25 June 1984 Publication History

Abstract

A new logic simulator called THEMISTM Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.

References

[1]
D.M. Schuler, et al, "A Program for the simulation and Concurrent Fault Simulation of Digital Circuits Described with Gate and Functional Models," Cherry Hill Test Conf. Proc., pp. 203-207, Cherry Hill, NJ (1979).
[2]
E. Ulrich and T. Baker, "The Concurrent Simulation of Nearly Identical Digital Networks," IEEE Computer (1974).
[3]
D.M. Schuler and R. Cleghorn, "An Efficient Method of Fault Simulation for Digital Circuits Modeled from Boolean Gates and Memories," 14th Design Automation Conf. Proc., pp. 230-238 (1977)
[4]
Melvin A. Breuer and Alice C. Parker, "Digital System Simulation: Current Status and Future Trends," 18th Design Automation Conf. Proc., pp. 269-275 (1981)
[5]
M. Abramovici, M. A. Breuer and K. Kumar, "Concurrent Fault Simulation and Functional Level Modeling," 14th Design Automation Conf. Proc., pp. 128-137 (1978)
[6]
R. Cleghorn, "PRIMEAIDS: An Integrated Electrical Design Environment," 18th Design Automation Conf. Proc., pp. 632-638 (1981)
[7]
R. McCann, "An Electronic Design Management System," AF-SD/INDUSTRY/NASA Conference and Workshops on Mission Assurance Proc., pp. F185-F192 (1983)

Cited By

View all
  • (1989)Formal Verification of Fault Tolerance Using Theorem-Proving TechniquesIEEE Transactions on Computers10.1109/12.2112338:3(366-376)Online publication date: 1-Mar-1989
  • (1985)An extensible object-oriented mixed-mod functional simulation systemProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317956(630-636)Online publication date: 1-Jun-1985

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '84: Proceedings of the 21st Design Automation Conference
June 1984
715 pages

Sponsors

Publisher

IEEE Press

Publication History

Published: 25 June 1984

Check for updates

Qualifiers

  • Article

Acceptance Rates

DAC '84 Paper Acceptance Rate 116 of 290 submissions, 40%;
Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)58
  • Downloads (Last 6 weeks)11
Reflects downloads up to 16 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (1989)Formal Verification of Fault Tolerance Using Theorem-Proving TechniquesIEEE Transactions on Computers10.1109/12.2112338:3(366-376)Online publication date: 1-Mar-1989
  • (1985)An extensible object-oriented mixed-mod functional simulation systemProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317956(630-636)Online publication date: 1-Jun-1985

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media