MICRO

There are several methods of executing programs written in a high level language. The most widely used is to compile the programs into machine language. Another is to translate the programs into some intermediate form and then to execute that form ...

This paper discusses the advantages of using high-level languages in the development of microcode. It also describes reasons functional programming languages should be considered as the source language for microcode compilers. The emergence of parallel ...

Unification is known to be the most repeated operation in logic programming and PROLOG interpreters. To speed up the execution of logic programs, the performance of unification must be improved. We propose a parallel unification machine for speeding up ...

This paper describes work in progress on the development of a direct execution Prolog processor.

Increasing the performance of application-specific processors by exploiting application-resident parallelism is often prohibited by costs; especially in the case of low-volume productions. The flexibility of horizontal-microcoded machines allows these ...

Combining is a local compiler optimization technique that can enhance the performance of global compaction techniques for VLIW machines. Given two adjacent operations of a certain class that are flow (read-after-write) dependent and that cannot be ...

The instruction systolic array (ISA) is a programmable parallel architecture suitable for VLSI implementation. This paper presents a generalization of the ISA, called the microprogrammed ISA, which uses simple microprogramming techniques. ...

The conventional design of electronic circuits is intolerant to operational faults. Self-checking logic is aimed at online fault detection and can hence be incorporated to achieve reliable operation. In this paper, the design of a self-checking ...

In a pipelined computer, there is a possibility of interaction between microwords. These interactions may cause the operation of the computer to slow down, or they may cause errors. An extended error checking tool is used to detect these cases and help ...

Effective and efficient testing of the control part of a processor has remained a difficult problem. While several approaches have been proposed in the literature for handling unaugmented control parts, they involve questionable assumptions, and the ...

The term peephole optimization is used to mean the pattern matching and conditional replacement performed on small sections of the intermediate form.

The circular dependence between the code generation phases implies that local optimals are rarely global ...

Only recently has the design of computer architectures deviated from the Von Neumann style. Most architectures based on the Von Neumann architecture suffer from what is called 'the semantic gap'. This means that the objects and operations in a high ...

Current software engineering practice heavily relies on the reliability of software implementation languages and underlying architectures. However, both the currently used languages, as well as the traditional architectures suffer from a shortage of ...

Loop optimization is an important aspect of microcode compaction to minimize execution time. In this paper a new loop optimization technique for horizontal microprograms is presented, which makes use of the cyclic regularity of loops.

We have extended ...

The problem of automatic loop parallelization has received a lot of attention in the area of parallelizing compilers. Automatic loop parallelization can be achieved by several algorithms. In this paper we address the problem of time optimal ...

A microprogramming teaching environment is presented. It is composed of a hardware part (a 16 bit microprogrammable processor) and a software part, running on a Macintosh II computer.

The software includes 6 modules: two microassemblers - one uses a ...

A new low-cost VLSI based microprogrammable computer system is described. This system is an ideal candidate for use in student microprogramming laboratories. The authors describe their experiences in using this computer.

Under timing constraints, local compaction may fail because of poor scheduling decisions. Su [SDWX87] uses foresight to avoid some of the poor scheduling decisions. However, the foresight takes a considerable amount of time. In this paper the ...

This paper first reviews the version shuffling problem for microcode compaction. Next, a somewhat representative compaction problem involving asymmetric ALUs and a port-limited register file is presented. Finally, the paper shows how to model the ...

This paper describes architectures based on a new memory structure. Memory systems which can perform multiple transfers are described and issues in processor architecture are considered. A general model for memory operations is given, and the classical ...

A new instruction fetch method, forward semantic, is offered to enable the deeply pipelined processors to fetch one useful instruction every cycle. Forward semantic is an improved alternative to the delayed branching (with or without squashing), with ...

This paper describes a method to reorder the straight line instruction streams for pipelined computers which have one instruction issue unit but may contain multiple function units. The objective is to make the most efficient usage of the pipelines ...

Models for the simulation of computer systems at the microarchitectural level are widely used to assist in design analysis and verification, and the development of microcode. The general model we describe here represents the behaviour of a clocked ...

The VAX Architecture provides hardware implementors with an opportunity or a nightmare, depending on your point of view. Such characteristics as 304 opcodes, a large number of addressing modes, a large number of supported data types, and non-...

This paper describes MIES, a design tool for the modeling, visualization, and analysis of VLSI microarchitectures. MIES combines a graphical data path model and symbolic control model and provides a number of user interfaces which allow these models to ...

Two major limitations concerning the design of cost-effective application-specific architectures are the recurrent costs of system-software development and hardware implementation, in particular VLSI implementation, for each architecture.

The SCalable ...

This paper presents the specification and implementation of a model oriented primarily to the evaluation of the structure of microarchitectures. According to the model, target architectures are described as an oriented graph which is examined by search ...

ASIC microprocessors are becoming an important technology for the control of complex (“embedded”) systems. The advantage of such microprocessors is that they can be tailored to the application. This tailoring is quite non-intuitive and optimization is a ...