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Miller factor for gate-level coupling delay calculation

Authors:

Pinhong Chen,

Desmond A. Kirkpatrick,

Kurt KeutzerAuthors Info & Claims

ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Pages 68 - 75

Published: 05 November 2000 Publication History

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Abstract

In coupling delay computation, a Miller factor of more than 2X may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5V_DD as the switching threshold voltage, an upper bound of 3X for maximum delay and a lower bound of -1X for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the Miller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations.

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Yang JLu KCho MYuan KPan DLin Y(2010)A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithographyProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899872(637-644)Online publication date: 18-Jan-2010
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Moiseev KKolodny AWimer S(2009)Power-delay optimization in VLSI microprocessors by wire spacingACM Transactions on Design Automation of Electronic Systems10.1145/1562514.156252314:4(1-28)Online publication date: 28-Aug-2009
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Information

Published In

ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

November 2000

558 pages

ISBN:0780364481

Conference Chair:
Ellen M. Sentovich
Cadence Berkley Labs., Berkley, California

Publisher

IEEE Press

Publication History

Published: 05 November 2000

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Article

Conference

ICCAD '00

Sponsor:

SIGDA

ICCAD '00: International Conference on Computer Aided Design

November 5 - 9, 2000

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

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Yang JLu KCho MYuan KPan DLin Y(2010)A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithographyProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899872(637-644)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899872
Moiseev KKolodny AWimer S(2009)Power-delay optimization in VLSI microprocessors by wire spacingACM Transactions on Design Automation of Electronic Systems10.1145/1562514.156252314:4(1-28)Online publication date: 28-Aug-2009
https://dl.acm.org/doi/10.1145/1562514.1562523
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https://dl.acm.org/doi/10.1145/1531542.1531661
Sinha DSchaeffer GAbbaspour SRubin ABorkam FNassif SRoychowdhury J(2008)Constrained aggressor set selection for maximum coupling noiseProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509627(790-796)Online publication date: 10-Nov-2008
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Yang JPan DNassif SRoychowdhury J(2008)Overlay aware interconnect and timing variation modeling for double patterning technologyProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509566(488-493)Online publication date: 10-Nov-2008
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Das DKillpack KKashyap CJas AZhou HKyung CChoi KHa S(2008)Pessimism reduction in coupling-aware static timing analysis using timing and logic filteringProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356922(486-491)Online publication date: 21-Jan-2008
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Moiseev KKolodny AWimer S(2008)Timing-aware power-optimal ordering of signalsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197313:4(1-17)Online publication date: 3-Oct-2008
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Xu JKhaled PChowdhury MNarayanan VYan ZMacii EBhanja S(2008)Fast bus waveform estimation at the presence of coupling noiseProceedings of the 18th ACM Great Lakes symposium on VLSI10.1145/1366110.1366190(339-342)Online publication date: 4-May-2008
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Muchherla KChen PMa DWang J(2008)A noniterative equivalent waveform model for timing analysis in presence of crosstalkACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442113:2(1-21)Online publication date: 23-Apr-2008
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Akl CBayoumi M(2008)Reducing interconnect delay uncertainty via hybrid polarity repeater insertionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200086116:9(1230-1239)Online publication date: 1-Sep-2008
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