research-article

Time bound control in a stochastic dynamic wafer fab

Authors:

Tao Zhang,

Falk Stefan Pappert,

Oliver RoseAuthors Info & Claims

WSC '16: Proceedings of the 2016 Winter Simulation Conference

Pages 2903 - 2911

Published: 11 December 2016 Publication History

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Abstract

Time bounds are a common constraint in wafer fabs. Releasing wafer into a time bound sequence leads to a tradeoff between capacity loss and yield loss due to violations. Two common approaches to tackle this challenge are static scheduling and dispatching rules. While static scheduling faces problems with the dynamic and stochastic nature of a wafer fab dispatching rules often lack the global perspective causing either unnecessary violations or capacity waste. In this paper, we present an approach taking elements of both these solution approaches to address time bound constraints and compare it to existing approaches.

References

[1]

Klemmt, A., and L. Mönch. 2012. "Scheduling Jobs with Time Constraints between Consecutive Process Steps in Semiconductor Manufacturing." In Proceedings of the 2012 Winter Simulation Conference, edited by C. Laroque, J. Himmelspach, R. Pasupathy, O. Rose and A.M. Uhrmacher, 1--10, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc. .

Digital Library

Google Scholar

[2]

Pappert, F. S., T. Zhang, J. Mager, F. Suhrke, and O. Rose. 2016. "Impact of Time Bound Constraints and Batching on Metallization in an Opto-semiconductor Fab." In Proceedings of the 2016 Winter Simulation Conference, edited by T. M. K. Roeder, P. I. Frazier, R. Szechtman, E. Zhou, T. Huschka and S. E. Chick, Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc. .

Digital Library

Google Scholar

[3]

Robinson, J. K. 1998. "Capacity Planning in A Semiconductor Wafer Fabrication Facility with Time Constraints between Process Steps." Ph.D. Thesis, Department of Mechanical & Industrial Engineering, University of Massachusetts Amherst.

Google Scholar

[4]

Robinson, J. K., and R. Giglio. 1999. "Capacity Planning for Semiconductor Wafer Fabrication with Time Constraints between Operations." In Proceedings of the 1999 Winter Simulation Conference, edited by P. A. Farrington, H. B. Nembhard, D. T. Sturrock and G. W. Evans, 880--887. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc. .

Digital Library

Google Scholar

[5]

Sadeghi, R., S. Dauzere-Peres, C. Yugma, and G. Lepelletier. 2015. "Production Control in Semiconductor Manufacturing with Time Constraints." In Proceedings of the Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI, edited by unknown, 29--33.

Google Scholar

[6]

Scholl, W., and J. Domaschke. 2000. "Implementation of Modeling and Simulation in Semiconductor Wafer Fabrication with Time Constraints between Wet Etch and Furnace Operations." IEEE Transactions on Semiconductor Manufacturing 13 (3):273--277.

Crossref

Google Scholar

[7]

Wang, H. K., C. F. Chien, and M. Gen. 2015. "An Algorithm of Multi-Subpopulation Parameters with Hybrid Estimation of Distribution for Semiconductor Scheduling with Constrained Waiting Time." IEEE Transactions on Semiconductor Manufacturing 28 (3):353--366.

Crossref

Google Scholar

[8]

Yu, T. S., H. J. Kim, C. Jung, and T. E. Lee. 2013. "Two-stage Lot Scheduling with Waiting Time Constraints and Due Dates." In Proceedings of the 2013 Winter Simulation Conference, edited by R. Pasupathy, S.-H. Kim, A. Tolk, R. Hill and M. E. Kuhl, 3630--3641. Piscataway, New Jersey: Institute of Electrical and Electronics Engineers, Inc.

Digital Library

Google Scholar

Cited By

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Kopp DHassoun MKalir AMönch L(2020)Integrating critical queue time constraints into SMT2020 simulation modelsProceedings of the Winter Simulation Conference10.5555/3466184.3466388(1813-1824)Online publication date: 14-Dec-2020
https://dl.acm.org/doi/10.5555/3466184.3466388
Pappert FZhang TRose OSuhrke FMager JFrey THuschka TChick S(2016)Impact of time bound constraints and batching on metallization in an opto-semiconductor fabProceedings of the 2016 Winter Simulation Conference10.5555/3042094.3042460(2947-2957)Online publication date: 11-Dec-2016
https://dl.acm.org/doi/10.5555/3042094.3042460

Time bound control in a stochastic dynamic wafer fab
1. Applied computing
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
    2. Online algorithms
      1. Online learning algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning

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Information & Contributors

Information

Published In

WSC '16: Proceedings of the 2016 Winter Simulation Conference

December 2016

3974 pages

ISBN:9781509044849

General Chair:
Todd Huschka
Mayo Clinic
,
Program Chair:
Stephen E. Chick
INSEAD

In-Cooperation

SAS
AnyLogic: The AnyLogic Company
Palgrave: Palgrave Macmillan
FlexSim: FlexSim Software Products, Inc.
ASA: American Statistical Association
IEEE/SMC: Institute of Electrical and Electronics Engineers: Systems, Man, and Cybernetics Society
Simio: Simio LLC
ODU: Old Dominion University
ASIM: Arbeitsgemeinschaft Simulation
ExtendSim: ExtendSim
NIST: National Institute of Standards & Technology
Amazon Simulations: Amazon Simulations

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IEEE Press

Publication History

Published: 11 December 2016

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WSC '16

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IIE
INFORMS-SIM
SIGSIM
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WSC '16: Winter Simulation Conference

December 11 - 14, 2016

Virginia, Arlington

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Overall Acceptance Rate 3,413 of 5,075 submissions, 67%

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Cited By

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Kopp DHassoun MKalir AMönch L(2020)Integrating critical queue time constraints into SMT2020 simulation modelsProceedings of the Winter Simulation Conference10.5555/3466184.3466388(1813-1824)Online publication date: 14-Dec-2020
https://dl.acm.org/doi/10.5555/3466184.3466388
Pappert FZhang TRose OSuhrke FMager JFrey THuschka TChick S(2016)Impact of time bound constraints and batching on metallization in an opto-semiconductor fabProceedings of the 2016 Winter Simulation Conference10.5555/3042094.3042460(2947-2957)Online publication date: 11-Dec-2016
https://dl.acm.org/doi/10.5555/3042094.3042460

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Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

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