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Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Published: 23 February 1998 Publication History

Abstract

This paper formalizes the synthesis process of wiring signature-invariant (WSI) combinational circuit mutants. The signature \sigma_0 is defined by a reference circuit \eta_0, which itself is modeled as a canonical form of a directed bipartite graph. A wiring perturbation \gamma induces a perturbed reference circuit \eta_{\gamma}. A number of mutant circuits \eta_{\gamma_i} can be resynthesized from the perturbed circuit \eta_\gamma. The mutants of interest are the ones that belong to the wiring-signature-invariant equivalence class {\cal N}_\sigma{}_0, i.e. the mutants \eta_{\gamma{}_i} \in {\cal N}_\sigma{}_0. Circuit mutants \eta_{\gamma{}_i} \in {\cal N}_\sigma{}_0 have a number of useful properties. For any wiring perturbation \gamma, the size of the wiring-signature-invariant equivalence class is huge. Notably, circuits in this class are not random, although for unbiased testing and benchmarking purposes, mutant selections from this class are typically random. For each reference circuit, we synthesized eight equivalence subclasses of circuit mutants, based on 0 to 100\% perturbation. Each subclass contains 100 randomly chosen mutant circuits, each listed in a different random order. The 14,400 benchmarking experiments with 3200 mutants in 4 equivalence classes, covering 13 typical EDA algorithms, demonstrate that an unbiased random selection of such circuits can lead to statistically meaningful differentiation and improvements of existing and new algorithms.

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cover image ACM Conferences
DATE '98: Proceedings of the conference on Design, automation and test in Europe
February 1998
940 pages

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IEEE Computer Society

United States

Publication History

Published: 23 February 1998

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Author Tags

  1. benchmarking
  2. circuit mutants
  3. equivalence class
  4. signature-invariance

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DATE98
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DATE98: Design, Automation & Test in Europe
February 23 - 26, 1998
Le Palais des Congrés de Paris, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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  • (2012)Hierarchical Benchmark Circuit Generation for FPGA Architecture EvaluationACM Transactions on Embedded Computing Systems10.1145/2331147.233115211:S2(1-25)Online publication date: 1-Aug-2012
  • (2008)Perturb+mutateACM Transactions on Reconfigurable Technology and Systems10.1145/1391732.13917361:3(1-24)Online publication date: 19-Sep-2008
  • (2001)Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing MinimizationACM Journal of Experimental Algorithmics10.1145/945394.9454026(8-es)Online publication date: 31-Dec-2001
  • (2000)Regression-based RTL power models for controllersProceedings of the 10th Great Lakes symposium on VLSI10.1145/330855.331025(147-152)Online publication date: 2-Mar-2000
  • (1999)Generation of very large circuits to benchmark the partitioning of FPGAProceedings of the 1999 international symposium on Physical design10.1145/299996.300026(67-73)Online publication date: 12-Apr-1999
  • (1998)Design of experiments in BDD variable orderingProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.289103(646-652)Online publication date: 1-Nov-1998

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