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Architectural simulation in the context of behavioral synthesis

Authors:

A. Jemai,

P. Kission,

A. A. JerrayaAuthors Info & Claims

DATE '98: Proceedings of the conference on Design, automation and test in Europe

Pages 590 - 595

Published: 23 February 1998 Publication History

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Abstract

This paper deals with integrating an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The resulting environment provides a cycle based simulation of a behavioral module under synthesis. The simulator and the behavioral synthesis are based on a single model that allows to link the behavioral description and the architecture produced by synthesis. The basic simulation-synthesis model is extended in order to allow for concurrent architectural simulation of several modules under synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

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Cited By

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Barbieri IBariani MScotto ARaggio M(2005)Multimedia terminal system-on-chip design and simulationEURASIP Journal on Advances in Signal Processing10.1155/ASP.2005.26942005(2694-2700)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1155/ASP.2005.2694
Barbieri IBariani MCabitto ARaggio M(2005)A Simulation and Exploration Technology for Multimedia-Application-Driven ArchitecturesJournal of VLSI Signal Processing Systems10.1007/s11265-005-6647-241:2(153-168)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1007/s11265-005-6647-2

Index Terms

Architectural simulation in the context of behavioral synthesis
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Model verification and validation
2. Hardware
  1. Electronic design automation
    1. Modeling and parameter extraction
  2. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checking of RTL generated through behavioral synthesis. The optimizations exploit the high-...

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DATE '98: Proceedings of the conference on Design, automation and test in Europe

February 1998

940 pages

ISBN:0818683597

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IEEE Computer Society

United States

Publication History

Published: 23 February 1998

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DATE98: Design, Automation & Test in Europe

February 23 - 26, 1998

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Cited By

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Barbieri IBariani MScotto ARaggio M(2005)Multimedia terminal system-on-chip design and simulationEURASIP Journal on Advances in Signal Processing10.1155/ASP.2005.26942005(2694-2700)Online publication date: 1-Jan-2005
https://dl.acm.org/doi/10.1155/ASP.2005.2694
Barbieri IBariani MCabitto ARaggio M(2005)A Simulation and Exploration Technology for Multimedia-Application-Driven ArchitecturesJournal of VLSI Signal Processing Systems10.1007/s11265-005-6647-241:2(153-168)Online publication date: 1-Sep-2005
https://dl.acm.org/doi/10.1007/s11265-005-6647-2

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Architectural tradeoffs with behavioral synthesis

Integration of behavioral and layout synthesis: a chip synthesis approach

Optimizing equivalence checking for behavioral synthesis