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A micro-architectural analysis of switched photonic multi-chip interconnects

Published: 09 June 2012 Publication History

Abstract

Silicon photonics is a promising technology to scale offchip bandwidth in a power-efficient manner. Given equivalent bandwidth, the flexibility of switched networks often leads to the assumption that they deliver greater performance than point-to-point networks on message passing applications with low-radix traffic patterns. However, when optical losses are considered and total optical power is constrained, this assumption no longer holds.
In this paper we present a power constrained method for designing photonic interconnects that uses the power characteristics and limits of optical switches, waveguide crossings, inter-layer couplers and waveguides. We apply this method to design three switched network topologies for a multi-chip system.
Using synthetic and HPC benchmark-derived message patterns, we simulated the three switched networks and a WDM point-to-point network. We show that switched networks outperform point-to-point networks only when the optical losses of switches and inter-layer couplers losses are each 0.75 dB or lower; achieving this would require a major breakthrough in device development. We then show that this result extends to any switched network with similarly complex topology, through simulations of an idealized "perfect" network that supports 90% of the peak bandwidth under all traffic patterns. We conclude that given a fixed amount of input optical power, under realistic device assumptions, a point-to-point network has the best performance and energy characteristics.

References

[1]
S. Beamer, C. Sun et al., "Re-architecting DRAM memory systems with monolithically integrated silicon photonics," in ISCA, 2010.
[2]
J. Chan, G. Hendry et al., "Architectural exploration of chip-scale photonic interconnection network designs using physical-layer analysis," J. Lightwave Tech., 2010.
[3]
D. Vantrease, R. Schreiber et al., "Corona: System implications of emerging nanophotonic technology," in ISCA, 2008.
[4]
Y. Pan, P. Kumar et al., "Firefly: illuminating future network-on-chip with nanophotonics," in ISCA, 2009.
[5]
A. Krishnamoorthy, R. Ho et al., "Computer systems based on silicon photonic interconnects," Proc. IEEE, 2009.
[6]
P. Koka, M. O. McCracken et al., "Silicon-photonic network architectures for scalable, power-efficient multi-chip systems," in ISCA, 2010.
[7]
A. Shacham, B. Lee et al., "Photonic NoC for DMA communications in chip multiprocessors," in HOTI, 2007.
[8]
AiDi Corp. (2011) Fiber array product details. {Online}. Available: http://www.aidicorp.com/
[9]
H. Rong, Y. Kuo et al., "High efficiency wavelength conversion of 10 gb/s data in silicon waveguides," Opt. Expr., vol. 14, no. 3, 2006.
[10]
R. Claps, D. Dimitropoulos et al., "Observation of stimulated raman amplification in silicon waveguides," in LEOS, vol. 1. IEEE, 2003, pp. 134--135.
[11]
E. Dulkeith, Y. Vlasov et al., "Self-phase-modulation in submicron silicon-on-insulator photonic wires," Opt. Expr., 2006.
[12]
I. Hsieh, X. Chen et al., "Cross-phase modulation in si photonic wire waveguides," in CLEO, 2006.
[13]
E. Dulkeith, F. Xia et al., "Group index and group velocity dispersion in silicon-on-insulator photonic wires," Opt. Expr., 2006.
[14]
M. Dinu, F. Quochi et al., "Third-order nonlinearities in silicon at telecom wavelengths," Appl. Phys. Lett, 2003.
[15]
W. Dally, B. Towles et al., Principles and Practices of Interconnection Networks. Morgan Kaufman, 2004.
[16]
H. Liu, H. Tam et al., "Low-loss waveguide crossing using a multimode interference structure," Opt. Comm., 2004.
[17]
F. Xu, A. Poon et al., "Silicon cross-connect filters using microring resonator coupled multimode-interference-based waveguide crossings," Opt. Expr., 2008.
[18]
P. Sanchis, P. Villalba et al., "Highly efficient crossing structure for silicon-on-insulator waveguides," Opt. Lett., 2009.
[19]
Y. Sakamaki, T. Saida et al., "Loss reduction of waveguide crossings by wavefront matching method and their application to integrated optical circuits," J. Q. Elec., 2009.
[20]
A. Krishnamoorthy, J. Cunningham et al., "Optical proximity communication with passively aligned silicon photonic chips," J. Q. Elec., 2009.
[21]
J. Yao, X. Zheng et al., "Grating-coupler based optical interlayer coupling," in IEEE Group IV Photonics, 2011.
[22]
F. Sun, J. Yu et al., "A 2 x 2 optical switch based on plasma dispersion effect in silicon-on-insulator," Opt. Comm., 2006.
[23]
J. Van Campenhout, W. Green et al., "Low-power, 2x2 silicon electro-optic switch with 110-nm bandwidth for broadband reconfigurable optical networks," Opt. Expr., 2009.
[24]
P. Dong, S. Liao et al., "Submilliwatt, ultrafast and broadband electro-optic silicon switches," Opt. Expr., 2010.
[25]
P. Dong, S. Preble et al., "All-optical compact silicon comb switch," Opt. Expr., 2007.
[26]
Y. Vlasov, W. Green et al., "High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks," Nature Photonics, vol. 2, no. 4, 2008.
[27]
X. Zheng, F. Liu et al., "Ultra-low power arrayed cmos silicon photonic transceivers for an 80 gbps wdm optical link," in National Fiber Optic Engineers Conference, 2011.
[28]
X. Zheng, P. Koka et al., "Silicon photonic WDM point-to-point network for multi-chip processor interconnects," in Group IV Photonics, 2008, pp. 380--382.
[29]
N. Kirman et al., "Leveraging optical technology in future bus-based chip multiprocessors," in MICRO, 2006.
[30]
C. Batten, A. Joshi et al., "Building many-core processor-to-dram networks with monolithic cmos silicon photonics," MICRO, vol. 29, no. 4, 2009.
[31]
G. Loh, "3d-stacked memory architectures for multi-core processors," in ISCA, 2008.
[32]
F. Petrini, W.-c. Feng et al., "The Quadrics network: high-performance clustering technology," in MICRO, 2002.
[33]
S. Scott, D. Abts et al., "The blackwidow high-radix Clos network," in ISCA, 2006.
[34]
K. D. Underwood, K. S. Hemmert et al., "A hardware acceleration unit for MPI queue processing," IPDPS, 2005.
[35]
T. Sugimoto, N. Komuro et al., "Maximum throughput analysis for rts/cts-used ieee 802.11 dcf in wireless multi-hop networks," in ICCCE, 2010.
[36]
R. A. Spanke, V. E. Benes et al., "N-stage planar optical permutation network," Appl. Opt., 1987.
[37]
P. Dong, W. Qian et al., "Low loss shallow-ridge silicon waveguides," Opt. Express, 2010.
[38]
C. Sun, C.-H. O. Chen et al., "DSENT - a tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling," in NOCS, 2012.
[39]
D. H. Bailey, L. Dagum et al., "NAS parallel benchmark results," in Supercomputing, 1992.
[40]
M. Geimer, F. Wolf et al., "A scalable tool architecture for diagnosing wait states in massively parallel applications," Parallel Comput., vol. 35, 2009.
[41]
G. Singh, T. Bhattacharjee et al., "Design of non-blocking and rearrangeable modified banyan network with electro-optic MZI switching elements," J. WASET, 2008.
[42]
H. Gu, K. H. Mo et al., "A low-power low-cost optical router for optical networks-on-chip in multiprocessor systems-on-chip," in ISVLSI, 2009.
[43]
N. Kirman, J. F. Martínez et al., "A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing," in ASPLOS, 2010.
[44]
J. Ahn, M. Fiorentino et al., "Devices and architectures for photonic chip-scale integration," Appl. Phys. A, 2009.
[45]
N. Binkert, A. Davis et al., "The role of optics in future high radix switch design," in ISCA, 2011.

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  • (2016)Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a ChipProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989111(377-386)Online publication date: 3-Oct-2016
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    cover image ACM Conferences
    ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
    June 2012
    584 pages
    ISBN:9781450316422
    • cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 40, Issue 3
      ISCA '12
      June 2012
      559 pages
      ISSN:0163-5964
      DOI:10.1145/2366231
      Issue’s Table of Contents

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    Published: 09 June 2012

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    ISCA '12 Paper Acceptance Rate 47 of 262 submissions, 18%;
    Overall Acceptance Rate 543 of 3,203 submissions, 17%

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    • (2018)Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPsACM Journal on Emerging Technologies in Computing Systems10.1145/315484014:1(1-27)Online publication date: 8-Mar-2018
    • (2016)Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a ChipProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989111(377-386)Online publication date: 3-Oct-2016
    • (2015)More is Less, Less is MoreACM SIGARCH Computer Architecture News10.1145/2786763.269437743:1(283-296)Online publication date: 14-Mar-2015
    • (2015)More is Less, Less is MoreACM SIGPLAN Notices10.1145/2775054.269437750:4(283-296)Online publication date: 14-Mar-2015
    • (2015)BandArbProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742876(1-8)Online publication date: 6-May-2015
    • (2015)More is Less, Less is MoreProceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/2694344.2694377(283-296)Online publication date: 14-Mar-2015
    • (2013)Wavelength stealingProceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/2540708.2540728(222-233)Online publication date: 7-Dec-2013
    • (2013)Software-defined massive multicore networking via freespace optical interconnectProceedings of the ACM International Conference on Computing Frontiers10.1145/2482767.2482802(1-9)Online publication date: 14-May-2013
    • (2019)A Survey of On-Chip Optical InterconnectsACM Computing Surveys10.1145/326793451:6(1-34)Online publication date: 28-Jan-2019
    • (2016)Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a ChipProceedings of the Second International Symposium on Memory Systems10.1145/2989081.2989111(377-386)Online publication date: 3-Oct-2016
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