research-article

The fast optimal voltage partitioning algorithm for peak power density minimization

Authors:

Jia Wang,

Shiyan HuAuthors Info & Claims

ICCAD '10: Proceedings of the International Conference on Computer-Aided Design

Pages 213 - 217

Published: 07 November 2010 Publication History

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Abstract

Increasing transistor density in nanometer integrated circuits has resulted in large on-chip power density. As a high-level power optimization technique, voltage partitioning is effective in mitigating power density. Previous works on voltage partitioning attempt to address it through minimizing total power consumption over all voltage partitions. Since power density significantly impacts thermal-induced reliability, it is also desired to directly mitigate peak power density during voltage partitioning. Unfortunately, none of the existing works consider this.

This paper proposes an efficient optimal voltage partitioning algorithm for peak power density minimization. Based on novel algorithmic techniques such as implicit power density binary search, the algorithm runs in O(n log n + m² log² n) time, where n refers to the number of functional units and m refers to the number of partitions/voltage levels. Our experimental results on large testcases demonstrate that large amount of (about 9.7x) reduction in peak power density can be achieved compared to a natural greedy algorithm, while the algorithm still runs very fast. It needs only 14.15 seconds to optimize 1M functional units.

References

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H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, "A provably good approximation algorithm for power optimization using multiple supply voltages," DAC, pp. 887--890, 2007.

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Cited By

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Wang JChen XLiu LHu SHu A(2012)Fast approximation for peak power driven voltage partitioning in almost linear timeProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429537(698-704)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429537
Wang JChen XLiao CHu SPhillips JHu AGraeb H(2011)The approximation scheme for peak power driven voltage partitioningProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132486(736-741)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132486

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Information & Contributors

Information

Published In

ICCAD '10: Proceedings of the International Conference on Computer-Aided Design

November 2010

863 pages

ISBN:9781424481927

General Chair:
Louis Scheffer
Howard Hughes Medical Institute, Ashburn, VA
,
Program Chairs:
Joel Phillips
Cadence Research Labs, Berkeley, CA
,
Alan J. Hu
Univ. of British Columbia, Vancouver, BC V6T 1Z4 Canada

Publisher

IEEE Press

Publication History

Published: 07 November 2010

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Conference

ICCAD '10

Sponsor:

SIGDA

ICCAD '10: The International Conference on Computer-Aided Design

November 7 - 11, 2010

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Wang JChen XLiu LHu SHu A(2012)Fast approximation for peak power driven voltage partitioning in almost linear timeProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429537(698-704)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429537
Wang JChen XLiao CHu SPhillips JHu AGraeb H(2011)The approximation scheme for peak power driven voltage partitioningProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132486(736-741)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132486

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The approximation scheme for peak power driven voltage partitioning

The approximation scheme for peak power driven voltage partitioning

Adaptive PSO-DV Algorithm for Minimization of Power Loss and Voltage Instability