Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology
Pages 255 - 260
Abstract
Minimum energy per operation is typically achieved in the subthreshold region where low speed and low robustness are two challenging problems. This paper studies the impact of Back Biasing (BB) schemes on these features for FDSOI technology. We show that Forward BB can help cover a wider design space in term of optimal frequency of operation while keeping minimum energy. Asymmetric BB between NMOS and PMOS can mitigate the effect of systematic mismatch on Minimum Energy Point (MEP) and robustness. With optimal asymmetric BB, we achieve either a MEP reduction up to 18% or a 36X speedup at the MEP.
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Index Terms
- Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology
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Published In
September 2013
440 pages
ISBN:9781479912353
- General Chairs:
- Pai Chou,
- Ru Huang,
- Program Chairs:
- Yuan Xie,
- Tanay Karnik
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IEEE Press
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Published: 04 September 2013
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ISLPED'13
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ISLPED'13: International Symposium on Low Power Electronics and Design
September 4 - 6, 2013
Beijing, China
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Overall Acceptance Rate 398 of 1,159 submissions, 34%
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