Improving processor hardware compiled cycle accurate simulation using program abstraction
Pages 186 - 194
Abstract
Verification is an important step in the development of real-time embedded systems. The validation of a real-time system uses a timing accurate simulator and, when the actual binary code is used, a cycle accurate simulator (CAS). However, a CAS is slow especially when the simulated processor is complex and the application is big. One way to improve the speed of a CAS is to use compiled simulation. In this scheme, the application binary code model is merged with the processor model. This allows to remove operations from the simulator and to speed up it. In this paper, we show how to use an abstraction of the program and improve the handling of functions calls. The resulted simulator is temporally and functionally equivalent. This technique improves simulation speed by more than 50% over the speed of an interpreted CAS.
References
[1]
F. Bellard. Qemu, a fast and portable dynamic translator. Translator, 394:41--46, 2005.
[2]
A. Bullich, M. Briday, J.-L. Béchennec, and Y. Trinquet. Comcas, a compiled cycle accurate simulation for hardware architecture. The Fifth International Conference on Advances in System Simulation (SIMUL'13), October 2013.
[3]
C. Cifuentes and V. Malhotra. Binary translation: Static, dynamic, retargetable? Proceedings International Conference on Software Maintenance, pages 340--349, 1996.
[4]
A. Fauth, J. Van Praet, and M. Freericks. Describing instruction set processors using nml. EDTC'95: Proceedings of the 1995 European Conference on Design and Test, pages 503--507, March 1995.
[5]
J. Gustafsson, A. Betts, A. Ermedahl, and B. Lisper. The Mälardalen WCET benchmarks -- past, present and future. In B. Lisper, editor, WCET2010, pages 137--147, Brussels, Belgium, July 2010. OCG.
[6]
G. Hadjiyiannis, S. Hanono, and S. Devadas. Isdl: an instruction set description language for retargetability. DAC'97: Proceedings of the 34th annual conference on Design automation, pages 299--302, 1997.
[7]
J. L. Hennessy and D. A. Patterson. Computer Architecture A Quantitative Approach-Second Edition. Morgan Kaufmann Publishers, Inc., 2001.
[8]
D. Jones and N. Topham. High speed cpu simulation using ltu dynamic binary translation. Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers, pages 50--64, January 2009.
[9]
R. Kassem, M. Briday, J.-L. Béchennec, G. Savaton, and Y. Trinquet. Simulator generation using an automaton based pipeline model for timing analysis. In International Multiconference on Computer Science and Information Technology (IMCSIT'08), pages 657--664, Wisla, Poland, October 2008.
[10]
R. Kassem, M. Briday, J.-L. Béchennec, G. Savaton, and Y. Trinquet. Harmless, a hardware architecture description language dedicated to real-time embedded system simulation. Journal of Systems Architecture - doi: http://dx.doi.org/10.1016/j.sysarc.2012.05.001 {retrieved: august, 2013}, pages 318--337, September 2011.
[11]
R. Kassem, M. Briday, J.-L. Béchennec, Y. Trinquet, and G. Savaton. Instruction set simulator generation using Harmless, a new hardware architecture description language. Simutools '09: Proceedings of the 2nd International Conference on Simulation Tools and Techniques, pages 24:1--24:9, 2009.
[12]
P. Mishra and N. Dutt, editors. Processor description languages. Morgan Kaufmann Publishers, 2008.
[13]
S. Pees, A. Hoffmann, V. Zivojnovic, and H. Meyr. Lisa - machine description language for cycle-accurate models of programmable dsp architectures. DAC'99: Proceedings of the 36th ACM/IEEE conference on design automation, pages 933--938, 1999.
[14]
W. Qin, S. Rajagopalan, and S. Malik. A formal concurrency model based architecture description language for synthesis of software development tools. In Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), pages 47--56, 2004.
[15]
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. Smarts: Accelerating microarchitecture simulation via rigorous statistical sampling. Proceedings of the 30th annual international symposium on Computer architecture, pages 84--95, June 2003.
Index Terms
- Improving processor hardware compiled cycle accurate simulation using program abstraction
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Published In
March 2014
211 pages
ISBN:9781631900075
- General Chair:
- Fernando Barros,
- Program Chairs:
- Kalyan Perumalla,
- Roland Ewald
Sponsors
- EAI: The European Alliance for Innovation
- Create-Net
- ICST
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ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)
Brussels, Belgium
Publication History
Published: 17 March 2014
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SIMUTools '14
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- EAI
SIMUTools '14: 7th International ICST Conference on Simulation Tools and Techniques
March 17 - 19, 2014
Lisbon, Portugal
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Overall Acceptance Rate 20 of 73 submissions, 27%
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