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Bit-alignment for retargetable code generators

Published: 20 May 1994 Publication History
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References

[1]
K. Schoofs, G. Goossens, H. De Man, "Bit-Alignment in Hardware Allocation for Multiplexed DSP Architectures", Proc EDAC 1993, p 289-293.
[2]
D. Lanneer, et al, "Architectural Synthesis for Medium and High Throughput Signal Processing with the new CATHEDRAL Environment", published in "High-Level VLSI Synthesis", edited by R.Camposano and W.Wolf, Kluwer, 1991.
[3]
K. Schoofs, G. Goossens, H. De Man, "Signal Type Optimisation in the design of time-multiplexed DSP- architectures.", Proc. EDAC 1994.
[4]
A.V. Aho, R. Sethi, J. D. Ullman, "Compilers, Techniques and Tools", Addison-Wesley Publishing Company, p344-247,359-364.
[5]
D. Genin, J. De Moortel, D. Desmet, E. Van de Velde, "System Design, Optimization and Intelligent Code Generation for Standard Digital Signal Processors.", Proc. ISCAS 1989, p 565-569.
[6]
J. Van Praet, G. Goossens, D. Lanneer, H. De Man, "Instruction Set Definition and Instruction Selection for ASIPs", Proc of High Level Synthesis Workshop, Ontario, 1994.

Cited By

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  • (1998)Code generation for compiled bit-true simulation for DSP applicationProceedings of the 11th international symposium on System synthesis10.5555/293016.293019(9-14)Online publication date: 2-Dec-1998

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cover image ACM Conferences
ISSS '94: Proceedings of the 7th international symposium on High-level synthesis
May 1994
169 pages
ISBN:0818657855

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 20 May 1994

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7HLSS94
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7HLSS94: 7th International Symposium on High Level Synthesis
May 18 - 20, 1994
Ontario, Niagra-on-the-Lake, Canada

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  • (1998)Code generation for compiled bit-true simulation for DSP applicationProceedings of the 11th international symposium on System synthesis10.5555/293016.293019(9-14)Online publication date: 2-Dec-1998

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