research-article

UPaRC: ultra-fast power-aware reconfiguration controller

Authors:

Hung-Manh Pham,

Sébastien Pillement,

Daniel ChilletAuthors Info & Claims

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1373 - 1378

Published: 12 March 2012 Publication History

Abstract

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers---up to 45 times more efficient.

References

[1]

J. Becker, M. Hubner, G. Hettich, R. Constapel, J. Eisenmann, and J. Luka, "Dynamic and Partial FPGA Exploitation," Proceedings of the IEEE, vol. 95, no. 2, pp. 438--452, 2007.

[2]

R. Viswanath, V. Wakharkar, A. Watwe, V. Lebonheur et al., "Thermal performance challenges from silicon to systems," Intel Technology Journal, 2000.

[3]

L. Sterpone, L. Carro, D. Matos, S. Wong, and F. Fakhar, "A New Reconfigurable Clock-Gating Technique for Low Power SRAM-based FPGAs," in Design, Automation Test in Europe, Grenoble, 2011, pp. 1--6.

[4]

J. Becker, M. Huebner, and M. Ullmann, "Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations," in Integrated Circuits and Systems Design, New York, 2003.

Digital Library

[5]

Xilinx, Inc., "Virtex-5 FPGA Config. User Guide UG191," 2009.

[6]

Xilinx, Inc., "LogiCORE IP XPS HWICAP DS586," 2010.

[7]

Xilinx, Inc., "MicroBlaze Processor Reference Guide UG081," 2011.

[8]

Xilinx, Inc., PowerPC 405 Processor Block Reference Guide, 2004.

[9]

M. Liu, W. Kuehn, Z. Lu, and A. Jantsch, "Run-Time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration," in Field Programmable Logic and Applications, Prague, 2009, pp. 498--502.

[10]

F. Duhem, F. Muller, and P. Lorenzini, "FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA," Reconfigurable Computing: Architectures, Tools and Applications, pp. 253--260, 2011.

Digital Library

[11]

A. Nabina and J. Nuñez-Yañez, "Dynamic Reconfiguration Optimisation with Streaming Data Decompression," in International Conference on Field Programmable Logic and Applications, Milano, 2010, pp. 602--607.

Digital Library

[12]

J. L. N. ez and S. Jones, "Gbits/s Lossless Data Compression Hardware," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, pp. 499--510, 2003.

Digital Library

[13]

I. Belaid, F. Muller, and M. Benjemaa, "New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA," International Journal of Reconfigurable Computing, pp. 65--67, 2010.

Digital Library

[14]

Xilinx, Inc., "LogiCORE IP Block Memory Generator v4.3."

[15]

M. Nelson and J. Gailly, The data compression book, M. Books, Ed., 1996, vol. 619.

[16]

Xilinx, Inc., Virtex-5 FPGA User-Guide, January 2009.

[17]

Xilinx, Inc., "ML505/ML506/ML507 Eval. Platform UG347," 2008.

[18]

Xilinx, Inc., "ML605 Hardware User Guide UG534," 2011.

Cited By

Gal BBromberg YRéveillère LSolanki J(2016)A Flexible SoC and Its Methodology for Parser-Based ApplicationsACM Transactions on Reconfigurable Technology and Systems10.1145/293937910:1(1-23)Online publication date: 24-Sep-2016
https://dl.acm.org/doi/10.1145/2939379
Bonamy RBilavarn SChillet DSentieys O(2014)Power consumption models for the use of dynamic and partial reconfigurationMicroprocessors & Microsystems10.1016/j.micpro.2014.01.00238:8(860-872)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.micpro.2014.01.002

Index Terms

UPaRC: ultra-fast power-aware reconfiguration controller
1. Hardware

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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

March 2012

1690 pages

ISBN:9783981080186

General Chairs:
Wolfgang Rosenstiel
University of Tuebingen and edacentrum, DE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE CEDA
The Russian Academy of Sciences: The Russian Academy of Sciences

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 12 March 2012

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DATE '12

Sponsor:

EDAA
EDAC
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The Russian Academy of Sciences

DATE '12: Design, Automation and Test in Europe

March 12 - 16, 2012

Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Gal BBromberg YRéveillère LSolanki J(2016)A Flexible SoC and Its Methodology for Parser-Based ApplicationsACM Transactions on Reconfigurable Technology and Systems10.1145/293937910:1(1-23)Online publication date: 24-Sep-2016
https://dl.acm.org/doi/10.1145/2939379
Bonamy RBilavarn SChillet DSentieys O(2014)Power consumption models for the use of dynamic and partial reconfigurationMicroprocessors & Microsystems10.1016/j.micpro.2014.01.00238:8(860-872)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.micpro.2014.01.002

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