research-article

Fast isomorphism testing for a graph-based analog circuit synthesis framework

Authors:

Markus Meissner,

Oliver Mitea,

Linda Luy,

Lars HedrichAuthors Info & Claims

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 757 - 762

Published: 12 March 2012 Publication History

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Abstract

This contribution presents a major improvement for our analog synthesis framework with an explorative characteristic. The presented approach in principle allows the synthesis of a wide range of circuits, without the limitation to specific circuit classes. Defined by a specification of up to 15 different performances, a fully sized, transistor level circuit is synthesized for a provided process technology. The presented work reduces the needed computational effort and thus drastically reduces the synthesis time, while adding new abstraction into the framework to provide an even wider range of synthesized circuits - demonstrated in experimental results.

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Cited By

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Sorkhabi SZhang L(2017)Automated topology synthesis of analog and RF integrated circuitsIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.01756:C(128-138)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.017
von Rosen JMeissner MHedrich LNebel WAtienza D(2015)Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog coresProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757024(912-915)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757024

Index Terms

Fast isomorphism testing for a graph-based analog circuit synthesis framework
1. Hardware

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Information

Published In

DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe

March 2012

1690 pages

ISBN:9783981080186

General Chairs:
Wolfgang Rosenstiel
University of Tuebingen and edacentrum, DE
,
Enrico Macii
Politecnico di Torino, IT

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 12 March 2012

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DATE '12

Sponsor:

EDAA
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SIGDA
The Russian Academy of Sciences

DATE '12: Design, Automation and Test in Europe

March 12 - 16, 2012

Dresden, Germany

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

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Sorkhabi SZhang L(2017)Automated topology synthesis of analog and RF integrated circuitsIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.01756:C(128-138)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.017
von Rosen JMeissner MHedrich LNebel WAtienza D(2015)Semiautomatic implementation of a bioinspired reliable analog task distribution architecture for multiple analog coresProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757024(912-915)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757024

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Recommendations

Advanced datapath synthesis using graph isomorphism

Fast analog circuit synthesis using sensitivity based near neighbor searches

Advanced datapath synthesis using graph isomorphism