article

Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory

Authors:

Naveen Neelakantam,

Craig ZillesAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 36, Issue 3

Pages 115 - 126

https://doi.org/10.1145/1394608.1382132

Published: 01 June 2008 Publication History

Abstract

We demonstrate how fine-grained memory protection can be used in support of transactional memory systems: first showing how a software transactional memory system (STM) can be made strongly atomic by using memory protection on transactionally-held state, then showing how such a strongly-atomic STM can be used with a bounded hardware TM system to build a hybrid TM system in which zero-overhead hardware transactions may safely run concurrently with potentially-conflicting software transactions. We experimentally demonstrate how this hybrid TM organization avoids the common-case overheads associated with previous hybrid TM proposals, achieving performance rivaling an unbounded HTM system without the hardware complexity of ensuring completion of arbitrary transactions in hardware. As part of our findings, we identify key policies regarding contention management within and across the hardware and software TM components that are key to achieving robust performance with a hybrid TM.

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Cited By

Litz HBraun BCheriton DZaks AMendelson BRauchwerger LHwu W(2016)EXCITE-VMProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967955(401-412)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2967955
Zhang MHuang JCao MBond M(2015)Low-overhead software transactional memory with progress guarantees and strong semanticsACM SIGPLAN Notices10.1145/2858788.268851050:8(97-108)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2858788.2688510
Zhang MHuang JCao MBond MCohen AGrove D(2015)Low-overhead software transactional memory with progress guarantees and strong semanticsProceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/2688500.2688510(97-108)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2688500.2688510
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Index Terms

Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory
1. Hardware
  1. Hardware validation
  2. Integrated circuits
    1. Semiconductor memory
2. Theory of computation
  1. Models of computation
    1. Concurrency
      1. Parallel computing models

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Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 36, Issue 3

June 2008

449 pages

ISSN:0163-5964

DOI:10.1145/1394608

Issue’s Table of Contents

ISCA '08: Proceedings of the 35th Annual International Symposium on Computer Architecture
June 2008
449 pages
ISBN:9780769531748

Copyright © 2008 Authors.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2008

Published in SIGARCH Volume 36, Issue 3

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Cited By

Litz HBraun BCheriton DZaks AMendelson BRauchwerger LHwu W(2016)EXCITE-VMProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967955(401-412)Online publication date: 11-Sep-2016
https://dl.acm.org/doi/10.1145/2967938.2967955
Zhang MHuang JCao MBond M(2015)Low-overhead software transactional memory with progress guarantees and strong semanticsACM SIGPLAN Notices10.1145/2858788.268851050:8(97-108)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2858788.2688510
Zhang MHuang JCao MBond MCohen AGrove D(2015)Low-overhead software transactional memory with progress guarantees and strong semanticsProceedings of the 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming10.1145/2688500.2688510(97-108)Online publication date: 24-Jan-2015
https://dl.acm.org/doi/10.1145/2688500.2688510
Titos-Gil JAcacio M(2015)Hardware Approaches to Transactional Memory in Chip MultiprocessorsHandbook on Data Centers10.1007/978-1-4939-2092-1_27(805-835)Online publication date: 17-Mar-2015
https://doi.org/10.1007/978-1-4939-2092-1_27
Scott M(2013)Shared-Memory SynchronizationSynthesis Lectures on Computer Architecture10.2200/S00499ED1V01Y201304CAC0238:2(1-221)Online publication date: 12-Jun-2013
https://doi.org/10.2200/S00499ED1V01Y201304CAC023
Yu XHe ZHong B(2012)A queuing model‐based approach for the analysis of transactional memory systemsConcurrency and Computation: Practice and Experience10.1002/cpe.286725:6(808-825)Online publication date: 10-Jul-2012
https://doi.org/10.1002/cpe.2867
Pusceddu MCeccolini STumeo APalermo GSciuto D(2011)Emulating transactional memory on FPGA multiprocessorsProceedings of the 24th international conference on Architecture of computing systems10.5555/1966221.1966231(74-85)Online publication date: 24-Feb-2011
https://dl.acm.org/doi/10.5555/1966221.1966231
Pusceddu MCeccolini STumeo APalermo GSciuto D(2011)Emulating Transactional Memory on FPGA MultiprocessorsArchitecture of Computing Systems - ARCS 201110.1007/978-3-642-19137-4_7(74-85)Online publication date: 2011
https://doi.org/10.1007/978-3-642-19137-4_7
Harris TLarus JRajwar R(2010)Transactional Memory, 2nd editionSynthesis Lectures on Computer Architecture10.2200/S00272ED1V01Y201006CAC0115:1(1-263)Online publication date: 22-Dec-2010
https://doi.org/10.2200/S00272ED1V01Y201006CAC011
Rossbach CHofmann OWitchel E(2010)Is transactional programming actually easier?ACM SIGPLAN Notices10.1145/1837853.169346245:5(47-56)Online publication date: 9-Jan-2010
https://dl.acm.org/doi/10.1145/1837853.1693462
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