research-article

Exploring power management in multi-core systems

Authors:

Reinaldo Bergamaschi,

Alper Buyuktosunoglu,

John DarringerAuthors Info & Claims

ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Pages 708 - 713

Published: 21 January 2008 Publication History

Abstract

Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

References

[1]

L. A. Barroso, "The price of performance". ACM Queue, vol. 3, no. 7, pp. 48--53, September 2005.

Digital Library

[2]

G. A. Paleologo, L. Benini, A. Bogliolo, and G. De Micheli, "Policy optimization for dynamic power management". In Proceedings of the Design Automation Conference (DAC'98), IEEE/ACM, pp. 182--187, San Francisco, June 15--19, 1998.

Digital Library

[3]

E. Grochowski, R. Ronen, J. Shen, and H. Wang, "Best of both latency and throughput". In Proceedings of IEEE International Conference on Computer Design (ICCD 2004), pp. 236--243, San Jose, October 11--13, 2004.

Digital Library

[4]

S. Heo, K. Barr and K. Asanovic, "Reducing power density through activity migration". In Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), pp. 217--222, Seoul, August 25--27, 2003.

Digital Library

[5]

M. Powell, M. Gomaa, and T. N. Vijaykumar, "Heat-and-run: leveraging SMT and CMP to manage power density through the operating system". In Proceedings of 11^th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), pp. 260--270, Boston, October 7--13, 2004.

Digital Library

[6]

E. Kursun, C. Y. Cher, A. Buyuktosunoglu, and P. Bose, "Investigating the effects of task scheduling on thermal behavior". 3^rd Workshop on Temperature-Aware Computer Systems (TACS'06), Boston, June 18, 2006.

[7]

K. Nowka, G. Carpenter, E. MacDonald, H. C. Ngo, B. Brock, K. Ishii, T. Nguyen, and J. Burns, "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling". IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1600--1608, November 2002.

[8]

G. Magklis, G. Semeraro, D. H. Albonesi, S. G. Dropsho, S. Dwarkadas, and M. L. Scott, "Dynamic frequency and voltage scaling for a multiple-clock-domain microprocessor". IEEE Micro, vol. 23, no. 6, pp. 62--68, Nov/Dec 2003.

Digital Library

[9]

R. McGowen, C. Poirier, C. Bostak, J. Ignowski, M. Millican, W. Parks, and S. Naffziger, "Power and temperature control on a 90-nm Itanium family processor". IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 229--237, January 2006.

[10]

C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi, "An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget". In Proceedings of the 39^th Annual International Symposium on Microarchitecure (MICRO'06), IEEE, pp. 347--358, Orlando, December 9--13, 2006.

Digital Library

[11]

S. Manne, A. Klauser, and D. Grunwald, "Pipeline gating: speculation control for energy reduction". In Proceedings of the 25^th International Symposium on Computer Architecture (ISCA'98), pp. 132--141, Barcelona, June/July 1998.

Digital Library

[12]

D. Brooks, P. Bose, V. Srinivasan, M. K. Gschwind, P. Emma, and M. Rosenfield, "New methodology for early-stage microarchitecture-level power-performance analysis of microprocessors". IBM Journal of Research & Development, vol. 47, no. 5/6, pp. 653--670, September/November 2003.

Digital Library

[13]

S. J. Wilton, and N. P. Jouppi, "CACTI: an enhanced cache access and cycle time model". IEEE Journal of Solid-State Circuits, vol. 31, no. 5, pp. 677--688, May 1996.

[14]

N. Magen, A. Kolodny, U. Weiser, and N. Shamir, "Interconnect-power dissipation in a microprocessor". In Proceedings of the 2004 International Workshop on System-Level Interconnect Prediction (SLIP'04), pp. 7--13, Paris, February 14--15, 2004.

Digital Library

[15]

T. Austin, E. Larson, D. Ernst, "SimpleScalar: an infrastructure for computer system modeling". IEEE Computer, vol. 35, no. 2, pp. 59--67, February 2002.

Digital Library

[16]

D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: a framework for architectural-level power analysis and optimization". In Proceedings of the 27^th annual international symposium on Computer architecture (ISCA 2000), pp. 83--94, Vancouver, June 10--14, 2000.

Digital Library

[17]

A. Bogliolo, L. Benini, E. Lattanzi, and G. De Micheli, "Specification and analysis of power-managed systems". Proceedings of the IEEE, vol. 92, no. 8, pp. 1308--1346, August 2004.

[18]

R. Bergamaschi, G. Han, A. Buyuktosunoglu, H. Patel, I. Nair, G. Janssen, G. Dittmann, N. Dhanwada, Z. Hu, P. Bose, J. Darringer, "Performance modeling for early analysis of multi-core systems." In Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2007), pp. 209--214, Salzburg, September 30--October 5, 2007.

Digital Library

[19]

J. Tendler, J. S. Dodson, J. S. Fields Jr., H. Le, B. Sinharoy, "POWER4 system microarchitecture". IBM Journal of Research & Development, vol. 46, no. 1, pp. 5--26, January 2002.

Digital Library

[20]

SPEC Standard Performance Evaluation Corporation, www.spec.org.

[21]

S. R. Kunkel, R. J. Eickemeyer, M. H. Lipasti, T. J. Mullins, B. O'Krafka, H. Rosenberg, S. P. VanderWiel, P. L. Vitale, and L. D. Whitley, "A performance methodology for commercial servers". IBM Journal of Research & Development, Vol.44, No.6, November, 2000.

Digital Library

[22]

"OPT++: an object-oriented nonlinear optimization library", http://csmr.ca.sandia.gov/opt++/

Cited By

Gebregirogis ATahoori M(2020)Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic SystemsACM Transactions on Design Automation of Electronic Systems10.1145/343649126:3(1-23)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3436491
Liu YCox GDeng QDraper SBianchini R(2017)Fast Power and Energy Management for Future Many-Core SystemsACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/30865042:3(1-31)Online publication date: 5-Sep-2017
https://dl.acm.org/doi/10.1145/3086504
Lampka KForsberg BFanucci LTeich J(2016)Keep it slow and in timeProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971896(385-390)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971896
Show More Cited By

Index Terms

Exploring power management in multi-core systems

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Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference

January 2008

812 pages

ISBN:9781424419227

General Chair:
Chong-Min Kyung,
Program Chairs:
Kiyoung Choi,
Soonhoi Ha

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEEK: The Institute of Electronics Engineers of Korea

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 21 January 2008

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Research-article

Conference

ASPDAC '08

Sponsor:

SIGDA
IEEK

ASPDAC '08: Asia and South Pacific Design Automation Conference

January 21 - 24, 2008

Seoul, Korea

Acceptance Rates

ASP-DAC '08 Paper Acceptance Rate 122 of 350 submissions, 35%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Gebregirogis ATahoori M(2020)Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic SystemsACM Transactions on Design Automation of Electronic Systems10.1145/343649126:3(1-23)Online publication date: 31-Dec-2020
https://dl.acm.org/doi/10.1145/3436491
Liu YCox GDeng QDraper SBianchini R(2017)Fast Power and Energy Management for Future Many-Core SystemsACM Transactions on Modeling and Performance Evaluation of Computing Systems10.1145/30865042:3(1-31)Online publication date: 5-Sep-2017
https://dl.acm.org/doi/10.1145/3086504
Lampka KForsberg BFanucci LTeich J(2016)Keep it slow and in timeProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971896(385-390)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971896
Sankaran SPalermo GFeo JTumeo AFranke H(2016)Predictive modeling based power estimation for embedded multicore systemsProceedings of the ACM International Conference on Computing Frontiers10.1145/2903150.2911714(370-375)Online publication date: 16-May-2016
https://dl.acm.org/doi/10.1145/2903150.2911714
Mariani GPalermo GZaccaria VSilvano C(2013)Design-space exploration and runtime resource management for multicoresACM Transactions on Embedded Computing Systems10.1145/2514641.251464713:2(1-27)Online publication date: 30-Sep-2013
https://dl.acm.org/doi/10.1145/2514641.2514647
Petrica PIzraelevitz AAlbonesi DShoemaker C(2013)FlickerACM SIGARCH Computer Architecture News10.1145/2508148.248592441:3(13-23)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485924
Petrica PIzraelevitz AAlbonesi DShoemaker CMendelson A(2013)FlickerProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485924(13-23)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485924
Bose PBuyuktosunoglu ADarringer JGupta MHealy MJacobson HNair IRivers JShin JVega AWeger ARosenstiel WMacii E(2012)Power management of multi-core chipsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492953(977-982)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492953
Bose PBuyuktosunoglu ACher CDarringer JGupta MHamann HJacobson HKudva PKursun EMadan NNair IRivers JShin JWeger AZyuban VBahar RLombardi FAtienza DBrunvand E(2010)Power-efficient, reliable microprocessor architecturesProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785551(299-304)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785551
Kandlur DKeller T(2009)Green data centers and hot chipsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1630139(888-890)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1630139

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