Systematic Scan Reconfiguration

A novel design-for-test (DFT) technique is presented for designing a core with a virtual scan chain which looks (to the system integrator) like it is shorter than the real scan chain inside the core. The I/O pins of a core with a virtual scan chain are ...

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, ...

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test ...