Article

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

Authors:

Antonio Deledda,

Matteo Pizzotti,

Luca Ciccarelli,

Pierluigi Rolandi,

Arseni Vitkovski,

Luca VanzoliniAuthors Info & Claims

DATE '07: Proceedings of the conference on Design, automation and test in Europe

Pages 9 - 14

Published: 16 April 2007 Publication History

Abstract

This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero over head for switching between successive configurations, relevant area and energy computational density on computational kernels (average of 2 GOPS/mm², 0.2GOPS/mW) and relatively small area occupation (18 mm²), making it suitable for acceleration or upgrade of multi-core heterogeneous embedded platforms. The processor is delivered with a software tool chain providing the application developer algorithmic analysis and design space exploration based on ANSI C, with no utilization of hardware-related constructs or description languages.

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Cited By

Yang CLiu LYin SWei SConstantinides GChen D(2015)Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689103(263-263)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689103
Voros NHübner MBecker JKühnle MThomaitiv FGrasset ABrelet PBonnot PCampi FSchüler ESahlbach HWhitty SErnst RBillich ETischendorf CHeinkel UIeromnimon FKritharidis DSchneider AKnaeblein JPutzke-Röming W(2013)MORPHEUSACM Transactions on Embedded Computing Systems10.1145/2442116.244212012:3(1-33)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442120
Rossi DMucci CCampi FSpolzino SVanzolini LSahlbach HWhitty SErnst RPutzke-Röming WGuerrieri R(2013)Application space exploration of a heterogeneous run-time configurable digital signal processorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218596321:2(193-205)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2185963
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A dynamically adaptive DSP for heterogeneous reconfigurable platforms
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Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '07: Proceedings of the conference on Design, automation and test in Europe

April 2007

1741 pages

ISBN:9783981080124

General Chair:
Rudy Lauwereins
IMEC and KULeuven, Belgium
,
Program Chair:
Jan Madsen
DTU, Denmark

Sponsors

The EDA Consortium
EDAA: European Design Automation Association
ECSI
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
IEEE Council on Electronic Design Automation (CEDA)
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

EDA Consortium

San Jose, CA, United States

Publication History

Published: 16 April 2007

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DATE07

Sponsor:

EDAA
SIGDA
The Russian Academy of Sciences

DATE07: Design, Automation and Test in Europe

April 16 - 20, 2007

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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DATE '25

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Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

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Citations

Cited By

Yang CLiu LYin SWei SConstantinides GChen D(2015)Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array (Abstract Only)Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689103(263-263)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689103
Voros NHübner MBecker JKühnle MThomaitiv FGrasset ABrelet PBonnot PCampi FSchüler ESahlbach HWhitty SErnst RBillich ETischendorf CHeinkel UIeromnimon FKritharidis DSchneider AKnaeblein JPutzke-Röming W(2013)MORPHEUSACM Transactions on Embedded Computing Systems10.1145/2442116.244212012:3(1-33)Online publication date: 8-Apr-2013
https://dl.acm.org/doi/10.1145/2442116.2442120
Rossi DMucci CCampi FSpolzino SVanzolini LSahlbach HWhitty SErnst RPutzke-Röming WGuerrieri R(2013)Application space exploration of a heterogeneous run-time configurable digital signal processorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2012.218596321:2(193-205)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1109/TVLSI.2012.2185963
Whitty SSahlbach HHurlburt BErnst RPutzke-Röming WDe Micheli GAl-Hashimi BMueller WMacii E(2010)Application-specific memory performance of a heterogeneous reconfigurable architectureProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871020(387-392)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871020
Ansaloni GBonzini PPozzi LBenini LDe Micheli GAl-Hashimi BMueller W(2009)Heterogeneous coarse-grained processing elementsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874752(542-547)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874752
Whitty SSahlbach HErnst RPutzke-Röming WBenini LDe Micheli GAl-Hashimi BMueller W(2009)Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architectureProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874630(27-32)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874630
Menard DCasseau EKhan SSentieys OChevobbe SGuyetant SDavid R(2009)Reconfigurable Operator Based Multimedia Embedded ProcessorProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_7(39-49)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_7
Deledda AMucci CVitkovski ABonnot PGrasset AMillet PKuehnle MRies FHuebner MBecker JCoppola MPieralisi LLocatelli RMaruccia GCampi FDeMarco TSciuto D(2008)Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processorProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403700(1352-1357)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403700
Mucci CVanzolini LCampi FToma MLauwereins RMadsen J(2007)Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architectureProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266441(355-360)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266441

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