Article

Free access

Architecture and implementation of a VLIW supercomputer

Authors:

James E. TornesAuthors Info & Claims

Supercomputing '90: Proceedings of the 1990 ACM/IEEE conference on Supercomputing

Pages 910 - 919

Published: 01 October 1990 Publication History

PDF eReader

Abstract

Very-Long-Instruction-Word (VLIW) computers achieve high performance by exploiting the fine-grain parallelism present in sequential or vectorizable code. Multiflow's /200 and /300 VLIW systems yielded near-supercomputer performance by this means despite the relatively slow (65 nS) clocks. With its much faster clock period (15 nS) and architectural improvements, the new /500 system attains approximately 4-9X the performance of its predecessors.

This paper describes the /500 architecture and implementation, with special attention paid to the tradeoffs involved in designing very high speed VLIWs.

References

[1]

R.P. Colwell, R.P. Nix, J.J~ O'Donnell, D.B. Papworth, P.K. Rodman, "A VLIW Architecture for a Trace Scheduling Compiler", IEEE Trans. on Comp., V. 37, N. 8, Aug. 1988.

Digital Library

Google Scholar

[2]

J.A. Fisher, "Very long instruction word architectures and the ELI-512" in Proc. lOth Syrup. Comput. Architecture, IEEE, June 1983, pp. 140-150.

Digital Library

Google Scholar

[3]

J.R. Ellis, Bulldog." A Compiler for VLIW Architectures. Cambridge, MA: MIT Press, 1986.

Digital Library

Google Scholar

[4]

Shigeo Kaneda, "A class of odd-weight-column SEC_D- ED_SbED codes for Memory system Applications", IEEE Trans. on Comp., V. 33, N. 8, August 1984.

Google Scholar

[5]

David Bailey, "Vector Computer Memory Bank Contention", IEEE Trans. on Comp., V. 36, N. 3, March 1987.

Digital Library

Google Scholar

[6]

N.P. Jouppi, D. W. Wall, "Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines", Proc. of the Third Intl. Conf. on Arch Support for Prog. Lang. and Operating Systems, April, 1989.

Digital Library

Google Scholar

[7]

William M. Johnson, "Super-Scalar Processor Design", Stanford University, Computer Systems Laboratory Technical Report No. CSL-TR-89-383, June 1989.

Digital Library

Google Scholar

[8]

R. Cohn, T. Gross, M. Lam, P.S. Tseng, "Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor",Proc, of the Third Intl. Conf. on Arch Support for Prog. Lang. and Operating Systems, April, 1989.

Digital Library

Google Scholar

[9]

K. Murakami, N. Irie, M. Kuga, S. Tomita, "StMP (Single Instruction stream/Multiple instruction Pipelining): A Novel High-Speed Single-Processor Architecture", Proceedings of the 16th intl. Syrup. on Comp. Arch,May 1989.

Digital Library

Google Scholar

[10]

H.B. Bakoglu, G.F. Grohoski, L.E. Thatcher, J.A. Kahle, C.R. Moore, D.P. Tuttle, W.E. Maule, W.R. Hardell, Jr., D.A. Hicks, M. Nguyenphu, R.K. Montoye, W.T. Glover, S. Dhawan, "IBM Second-Generation RISC Machine Organization", Proceedings of the 1989 IEEE International Conference on Computer Design, Oct. 1989.

Google Scholar

[11]

G.S. Sohi, S. Vajapeyam, "Tradeoffs in Instruction Format Design for Horizontal Architectures", Proc. of the Third Intl. Conf.on Arch. Support for Prog. Lang. and Operating Systems, April, 1989.

Digital Library

Google Scholar

[12]

Olaf Lubeck, "Supercomputer Performance: The Theory, Practice, and Results", Los Alamos National Laboratory, Technical Report LA-11204-MS, January 1988.

Google Scholar

[13]

J.E. Smith, "Dynamic Instruction Scheduling and the Astronautics ZS-I", IEEE Computer, July 1989.

Digital Library

Google Scholar

[14]

Robert Herndon, private communication, Cray Computer Corp., July 1990.

Google Scholar

Cited By

View all

Chu MMahlke S(2007)Code and data partitioning for fine-grain parallelismACM SIGPLAN Notices10.1145/1273444.125479842:7(161-164)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254798
Chu MMahlke SPande SLi Z(2007)Code and data partitioning for fine-grain parallelismProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254798(161-164)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254798
Chu MMahlke S(2006)Compiler-directed Data Partitioning for Multicluster ProcessorsProceedings of the International Symposium on Code Generation and Optimization10.1109/CGO.2006.9(208-220)Online publication date: 26-Mar-2006
https://dl.acm.org/doi/10.1109/CGO.2006.9
Show More Cited By

Index Terms

Recommendations

A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into ...
A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into ...
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm

This paper presents a cost-effective and high-performance dual-thread VLIW processor model. The dual-thread VLIW processor model is a low-cost subset of the Weld architecture paradigm. It supports one main thread and one speculative thread running ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

Supercomputing '90: Proceedings of the 1990 ACM/IEEE conference on Supercomputing

November 1990

982 pages

ISBN:0897914120

Co-chairs:
Daniel V. Pryor
Supercomputing Research Center
,
Gary Montry
Myrias Computer Corporation
,
General Chair:
Joanne L. Martin
IBM Corporation

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 October 1990

Check for updates

Qualifiers

Article

Conference

SC '90

Sponsor:

SIGARCH
IEEE-CS

SC '90: International Conference for High Performance Computing, Networking, Storage and Analysis

November 12 - 16, 1990

New York, New York, USA

Acceptance Rates

Overall Acceptance Rate 1,516 of 6,373 submissions, 24%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

24
Total Citations
View Citations
895
Total Downloads

Downloads (Last 12 months)99
Downloads (Last 6 weeks)9

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Chu MMahlke S(2007)Code and data partitioning for fine-grain parallelismACM SIGPLAN Notices10.1145/1273444.125479842:7(161-164)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254798
Chu MMahlke SPande SLi Z(2007)Code and data partitioning for fine-grain parallelismProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254798(161-164)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254798
Chu MMahlke S(2006)Compiler-directed Data Partitioning for Multicluster ProcessorsProceedings of the International Symposium on Code Generation and Optimization10.1109/CGO.2006.9(208-220)Online publication date: 26-Mar-2006
https://dl.acm.org/doi/10.1109/CGO.2006.9
Chuang WCalder BFerrante JJohnson RConte THwu W(2003)Phi-Predication for light-weight if-conversionProceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization10.5555/776261.776281(179-190)Online publication date: 23-Mar-2003
https://dl.acm.org/doi/10.5555/776261.776281
Lapinskii VJacome Mde Veciana GRabaey J(2001)High-quality operation binding for clustered VLIW datapathsProceedings of the 38th annual Design Automation Conference10.1145/378239.379051(702-707)Online publication date: 22-Jun-2001
https://dl.acm.org/doi/10.1145/378239.379051
Mattson PDally WRixner SKapasi UOwens J(2000)Communication schedulingACM SIGOPS Operating Systems Review10.1145/384264.37900534:5(82-92)Online publication date: 12-Nov-2000
https://dl.acm.org/doi/10.1145/384264.379005
Mattson PDally WRixner SKapasi UOwens J(2000)Communication schedulingACM SIGARCH Computer Architecture News10.1145/378995.37900528:5(82-92)Online publication date: 12-Nov-2000
https://dl.acm.org/doi/10.1145/378995.379005
Mattson PDally WRixner SKapasi UOwens JRudolph LGupta A(2000)Communication schedulingProceedings of the ninth international conference on Architectural support for programming languages and operating systems10.1145/378993.379005(82-92)Online publication date: 12-Nov-2000
https://dl.acm.org/doi/10.1145/378993.379005
Mattson PDally WRixner SKapasi UOwens J(2000)Communication schedulingACM SIGPLAN Notices10.1145/356989.35699735:11(82-92)Online publication date: 1-Nov-2000
https://dl.acm.org/doi/10.1145/356989.356997
Nystrom EEichenberger ABondi JSmith J(1998)Effective cluster assignment for modulo schedulingProceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture10.5555/290940.290966(103-114)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.5555/290940.290966
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

A VLIW architecture for a trace scheduling compiler

A VLIW architecture for a trace scheduling compiler

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm