Article

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems

Authors:

Achim Rettberg,

Mauro Zanella,

Christophe Bobda,

Thomas LehmannAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 11130

Published: 03 March 2003 Publication History

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Abstract

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References

[1]

{1} H. M. Jacobson; P. N. Kudva; P. Brose; P. W. Cook; S. E. Schuster; E. G. Mercer; C. J. Myers. "Synchronous Interlocked Pipelines", 8th International Symposium on Asynchronous Circuits and Systems (ASYNC 02), Manchester, UK, April 2002.

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[2]

{2} St. M. Shinners. "Modern control system theory and design", John Wiley & Sons, New York/Chichester, 2nd ed., 1998.

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[3]

{3} A. Rettberg; A. Hennig; B. Kleinjohann. "Re-Configurable Multiplier Units of the Asynchronous FLYSIG Architecture", 10th NASA Symposium on VLSI Design, Albuquerque, NM, USA, March 2002.

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[4]

{4} M. Zanella; M. Robrecht; Th. Lehmann; R. Gielow; A. de Freitas Francisco; A. Horst. "RABBIT: A Modular Rapid Prototyping Platform for Distributed Mechatronic Systems", SBCCI 2001 - XIV Symposium on Integrated Circuits and Systems Design, Brasília, Brazil.

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Cited By

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Weber RRettberg A(2009)Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined ArchitectureProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_37(330-335)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_37
Dittmann FRettberg AWeber RPetraglia APedroni VCauwenberghs G(2007)Optimization techniques for a reconfigurable, self-timed, and bit-serial architectureProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284526(153-158)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284526
Giefers HRettberg ACoelho CJacobi RBecker J(2006)Energy aware multiple clock domain scheduling for a bit-serial, self-timed architectureProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150377(113-118)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150377
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Index Terms

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems
1. Computer systems organization
2. Hardware
  1. Hardware test
  2. Robustness

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Information

Published In

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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DATE03

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SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Weber RRettberg A(2009)Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined ArchitectureProceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications10.1007/978-3-642-00641-8_37(330-335)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1007/978-3-642-00641-8_37
Dittmann FRettberg AWeber RPetraglia APedroni VCauwenberghs G(2007)Optimization techniques for a reconfigurable, self-timed, and bit-serial architectureProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284526(153-158)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284526
Giefers HRettberg ACoelho CJacobi RBecker J(2006)Energy aware multiple clock domain scheduling for a bit-serial, self-timed architectureProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150377(113-118)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150377
Dittmann FRettberg AWeber R(2005)Path concepts for a reconfigurable bit-serial synchronous architectureProceedings of the 2005 international conference on Embedded and Ubiquitous Computing10.1007/11596356_46(448-457)Online publication date: 6-Dec-2005
https://dl.acm.org/doi/10.1007/11596356_46

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Recommendations

Low-power digit-serial and bit-serial dsp systems

Bit-Serial Multipliers and Squarers

Optimization of NULL convention self-timed circuits