Article

A Lightweight Approach for Embedded Reconfiguration of FPGAs

Authors:

Brandon Blodget,

Scott McMillan,

Patrick LysaghtAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Page 10399

Published: 03 March 2003 Publication History

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Abstract

This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

Cited By

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Hong CBenkrid KIsa NIturbe X(2014)A run-time reconfigurable system for adaptive high performance efficient computingACM SIGARCH Computer Architecture News10.1145/2641361.264138041:5(113-118)Online publication date: 18-Jun-2014
https://dl.acm.org/doi/10.1145/2641361.2641380
Quadri IMeftali SDekeyser J(2009)High level modeling of dynamic reconfigurable FPGAsInternational Journal of Reconfigurable Computing10.1155/2009/4086052009(1-15)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/408605
Rathgeb CPeterson G(2009)Secure processing using dynamic partial reconfigurationProceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies10.1145/1558607.1558674(1-4)Online publication date: 13-Apr-2009
https://dl.acm.org/doi/10.1145/1558607.1558674
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Index Terms

A Lightweight Approach for Embedded Reconfiguration of FPGAs
1. Computer systems organization
2. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs

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Information & Contributors

Information

Published In

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

March 2003

1112 pages

ISBN:0769518702

Publisher

IEEE Computer Society

United States

Publication History

Published: 03 March 2003

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Conference

DATE03

Sponsor:

SIGDA

DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all

Hong CBenkrid KIsa NIturbe X(2014)A run-time reconfigurable system for adaptive high performance efficient computingACM SIGARCH Computer Architecture News10.1145/2641361.264138041:5(113-118)Online publication date: 18-Jun-2014
https://dl.acm.org/doi/10.1145/2641361.2641380
Quadri IMeftali SDekeyser J(2009)High level modeling of dynamic reconfigurable FPGAsInternational Journal of Reconfigurable Computing10.1155/2009/4086052009(1-15)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1155/2009/408605
Rathgeb CPeterson G(2009)Secure processing using dynamic partial reconfigurationProceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies10.1145/1558607.1558674(1-4)Online publication date: 13-Apr-2009
https://dl.acm.org/doi/10.1145/1558607.1558674
Paulsson KHübner MBecker JSciuto D(2008)Cost-and power optimized FPGA based system integrationProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403390(50-55)Online publication date: 10-Mar-2008
https://dl.acm.org/doi/10.1145/1403375.1403390
Tan HDeMara R(2008)A multilayer framework supporting autonomous run-time partial reconfigurationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.91755116:5(504-516)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2008.917551
Pellizzoni RCaccamo M(2007)Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded SystemsIEEE Transactions on Computers10.1109/TC.2007.7076356:12(1666-1680)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1109/TC.2007.70763
Hübner MSchuck CBecker J(2006)Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899145(196-196)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1899145
Paulsson KHübner MBecker JCoelho CJacobi RBecker J(2006)On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitivesProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150389(173-178)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150389
Hübner MBecker JCoelho CJacobi RBecker J(2006)Exploiting dynamic and partial reconfiguration for FPGAsProceedings of the 19th annual symposium on Integrated circuits and systems design10.1145/1150343.1150350(1-4)Online publication date: 28-Aug-2006
https://dl.acm.org/doi/10.1145/1150343.1150350
Eskinazi RLima MMaciel PValderrama CFilho ANascimento P(2005)A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable SystemsProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.72Online publication date: 4-Apr-2005
https://dl.acm.org/doi/10.1109/IPDPS.2005.72
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