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Mark Heinrich
Associate
Professor Department of Computer Science
Mailing Address: CS Department, University of Central Florida 4000 Central Florida Blvd. Orlando, FL 32816-2362
Email: heinrich @ cs.ucf.edu Office: HEC 345 Phone: (407) 882-0138 |
Research Interests
| Parallel computer architecture, heteroegenous architectures, active memory and I/O systems, scalable cache coherence protocols, multiprocessor simulation methodology, hardware/software co-design, and scalable web services. |
Bio
| I am currently an Associate Professor in Computer Science at UCF. After the creation of the School of EECS in 2005, I served as its Associate Director from 2005-2007. Before
the merge I was Director of the School of Computer Science
from April to September, 2005. I came to UCF as an Associate
Professor in January, 2003. Prior to that, I was
an Assistant Professor in the School of Electrical and
Computer Engineering at Cornell
University, a co-founder of its Computer
Systems Laboratory, and a member of the Intelligent
Information Systems Institute. I received my Ph.D. in Electrical
Engineering from Stanford University
under John Hennessy in
1998 where I was a principal designer of the FLASH
multiprocessor; the author of FlashLite, the system-level simulator of
the FLASH machine; and the designer of four cache coherence protocols for
FLASH (bitvector/coarsevector, dynamic pointer allocation, SCI, and a
simple two-bit protocol. I received my Bachelor of Science in
Electrical Engineering and Computer Science from Duke
University in 1991. I was co-founder and CTO of Phanfare, Inc., an archival photo and video hosting service, now part of Carbonite. I was also the co-founder and Chief Architect of
Flashbase, Inc. an Internet company specializing in automated sweepstakes
and database-backed forms and tools for customer acquisition. Flashbase was acquired by DoubleClick in 2000.
Oh, I am a HUGE sports fan. I am also a huge history buff and have visited the grave of every US President. |
Teaching
| Spring 2020: | ||
| COP 4934 CS Senior Design I MW 12:00-1:15pm Room: CB1 104 | ||
| COP 4935 CS Senior Design II MW 01:30-2:45pm Room: CB1 104 | ||
| Office Hours: MW 3:30pm-5:00pm (for Sr. Design), TR 1:00-4:00pm (for Undergrad Coordinator Walk-ins) Room: HEC 345 |
Publications
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C. E. Giles, C. Peterson and M. Heinrich. "A Fast Discrete Event Driven Simulation Methodology for Computer Architectural Simulation". IEEE 20th International Conference on High Performance Computing and Communications (HPCC), pp. 510-517, June 2018. (PDF) G. Mackey, M. Agun, M. Heinrich, R. Ryan, J. Yu. "Igloos Make the Cold Bearable: A Novel HDD Technology for Cold Storage". IEEE 20th International Conference on High Performance Computing and Communications (HPCC), June 2018. (PDF) C. E. Giles and M. Heinrich. "M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU Systems". IEEE International Conference on Computer Design (ICCD), pp. 477-484, November 2017. (PDF) Loundy, K., Schaefer, L., Foran, A., Ninah, C. et al., "A Distributed Simulation of a Martian Fuel Production Facility". SAE Technical Paper 2017-01-2022, 2017, doi:10.4271/2017-01-2022. (PDF) D. D. Kalamkar, M. Chaudhuri, and M. Heinrich. "Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads". IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007. (PDF) M.Chaudhuri and M. Heinrich. "Integrated Memory Controllers with Parallel Coherence Streams". IEEE Transactions on Parallel and Distributed Systems (TPDS)), 18(8):1159-1173, August 2007. (PDF) M.Chaudhuri and M. Heinrich. "Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols". IEEE Transactions on Parallel and Distributed Systems (TPDS)), 15(8):699-712, August 2004. (PDF) M.Chaudhuri and M. Heinrich. "SMTp: An Architecture for Next-generation Scalable Multi-threading". In Proceedings of the 31st International Symposium on Computer Architecture (ISCA)), pages 124-135, June 2004. (PDF) D. Kim, M.Chaudhuri, M. Heinrich, and E. Speight. "Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems". IEEE Transactions on Computers, 53(3):288-307, March 2004. (PDF) M. Chaudhuri, and M. Heinrich. "The Impact of Negative Acknowledgments in Shared Memory Scientific Applications". IEEE Transactions on Parallel and Distributed Systems (TPDS), 15(2):134-150, February 2004. (PDF) M. Hao and M. Heinrich. "Exploiting Active CMP-based Devices in System Area Networks". 3rd Workshop on System Area Networks (SAN-3), held in conjunction with HPCA, February 2004. (PDF) M. Chaudhuri, M. Heinrich, C. Holt, et al. "Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation". IEEE Transactions on Computers, 52(7):862-880, July 2003. (PDF) M. Heinrich and M. Chaudhuri. "Ocean Warning: Avoid Drowning". ACM SIGARCH Computer Architecture News, 31(3):30-32, June 2003. (PDF) D. Kim, M. Chaudhuri, and M. Heinrich. "Active Memory Techniques for ccNUMA Multiprocessors". In Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS)), April 2003. (PDF) M. Hao and M. Heinrich. "Active I/O Switches in System Area Networks". In Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 365-376, February 2003. (PDF) D. Kim, M. Chaudhuri, and M. Heinrich. "Leveraging Cache Coherence in Active Memory Systems". In Proceedings of the 16th International Conference on Supercomputing (ICS), pages 2-13, June 2002. (PDF) M. Chaudhuri, D. Kim, and M. Heinrich. "Cache Coherence Protocol Design for Active Memory Systems". In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), pages 83-89, June 2002. (PDF) M. Heinrich, E. Speight, and M. Chaudhuri. "Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters". In Proceedings of the Fourth International Symposium on High-Performance Computing (ISHPC), Lecture Notes in Computer Science, vol. 2327, Springer-Verlag, pages 78-92, May 2002. (PDF) M. Heinrich and E. Speight. "Providing Hardware DSM Performance at Software DSM Cost". Cornell Computer Systems Lab Technical Report CSL-TR-2000-1008, November 2000 (PDF) J. Gibson, R. Kunz, D. Ofelt, M. Horowitz, J. Hennessy, and M. Heinrich. "FLASH vs. (Simulated) FLASH: Closing the Simulation Loop". In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 49-58, November 2000 (PDF) A. Chou, B. Chelf, D. Engler, and M. Heinrich. "Using Meta-Level Compilation to Check FLASH Protocol Code". In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 59-70, November 2000 (PDF) R. Manohar and M. Heinrich. "A Case For Asynchronous Active Memories". ISCA 2000 Solving the Memory Wall Problem Workshop, June 2000 (PDF) R. Manohar and M. Heinrich. "The Branch Processor Architecture". Cornell Computer Systems Lab Technical Report CSL-TR-1999-1000, November 1999 (PDF) J. Hennessy, A. Gupta, and M. Heinrich, "Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges". Proceedings of the IEEE, 87(3):418-429, Special Issue on Distributed Shared Memory, March 1999 (PDF) M. Heinrich, R. Soundararajan, J. Hennessy, and A. Gupta, "A Quantitatitve Analysis of the Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols". IEEE Transactions on Computers, 48(2):205-217, Special Issue on Cache Memory and Related Problems, February 1999 (PDF) M. Heinrich, "The Performance and Scalability of Distributed Shared Memory Cache Coherence Protocols". Ph.D. Dissertation, Stanford University, October 1998. (PDF) R. Soundararajan, M. Heinrich, B. Verghese, et al. "Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors". In Proceedings of the 25th International Symposium on Computer Architecture (ISCA), pages 342-355, June 1998. (PDF) K. Olukotun, M. Heinrich, and D. Ofelt, "Digital System Simulation: Methodologies and Examples". In Proceedings of the 35th Design Automation Conference (DAC), pages 658-663, June 1998 (PDF) M. Heinrich, D. Ofelt, M. Horowitz, and J. Hennessy, "Hardware/Software Codesign of the Stanford FLASH Multiprocessor". In Proceedings of the IEEE Special Issue on Hardware/Software Co-design, Vol. 85, No. 3, March 1997 (PDF) M. Martonosi, D. Ofelt, and M. Heinrich, "Integrating Performance Monitoring and Communication in Parallel Computers". In ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, pp. 138-147, May 1996 (PDF) J. Hennessy and M. Heinrich, "Hardware/Software Co-Design of Processors: Concepts and Examples". In Hardware/Software Co-design, edited by G. de Micheli and M. Sami, Dordecht; Boston: Kluwer Academic Publishers, c. 1996 (PDF) C. Holt, M. Heinrich, J.P. Singh, et al., "The Effects of Latency, Occupancy, and Bandwidth in Distributed Shared Memory Multiprocessors". Stanford University Technical Report CSL-TR-95-660, January 1995 (PDF) M. Heinrich, J. Kuskin, D. Ofelt, et al., "The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor". In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 274-285, 1994 (PDF) J. Kuskin, D. Ofelt,
M. Heinrich, et al., "The
Stanford FLASH Multiprocessor". In Proceedings of the 21st
International Symposium on Computer Architecture (ISCA), pages
302-313, April 1994 (PDF)
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Academic Genealogy
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John Hennessy, Ph.D. 1977, SUNY Stony Brook |