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A Radiation-Tolerant 25.6-Gb/s High-Speed Transmitter in 28-nm CMOS With a Tolerance of 1 Grad
/ Klekotko, A (CERN ; Leuven U.) ; Biereigel, S (CERN) ; Baszczyk, M (CERN) ; Moreira, P (CERN) ; Martina, F (CERN) ; Prinzie, J (Leuven U.) ; Kulis, S (Leuven U.)
This article presents a 25.6-Gbit $\cdot $ s−1 high-speed transmitter (HST) manufactured using 28-nm CMOS technology. The HST macroblock includes an all-digital phase-locked loop (ADPLL), duty cycle corrector (DCC) circuit, data pattern generator, serializer, and a driver capable of driving the differential 100- $\Omega $ line as well as a silicon photonics (SiPh) ring modulator (RM). [...]
2024 - 9 p.
- Published in : IEEE Trans. Nucl. Sci. 71 (2024) 2124-2132
Fulltext: PDF;
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Overview of the production and qualification tests of the lpGBT
/ Hernandez Montesinos, D (CERN) ; Baron, S (CERN) ; Biereigel, S (CERN) ; Hazell, P (CERN) ; Kulis, S (CERN) ; Vicente Leitao, P (CERN) ; Moreira, P (CERN) ; Porret, D (CERN) ; Wyllie, K (CERN)
The Low-Power Gigabit Transceiver (lpGBT) is a radiation-tolerant ASIC used in high-energy physics experiments for multipurpose high-speed bidirectional serial links. Around 200,000 chips have been tested with a production test system capable of exercising the majority of the ASIC functionality to ensure its correct operation.Furthermore, specific individual qualification tests were carried out beyond the production tester limits, including radiation, multi-drop bus topology, inter-chip communication through different types of electrical links and characterization of jitter and stability of the recovered clocks.In this article, an overview of the production and qualification tests is given together with their results demonstrating the robustness and flexibility of the lpGBT..
2024 - 8 p.
- Published in : JINST
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C04048
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Digital duty-cycle correction circuit for clock paths in radiation-tolerant high-speed wireline transmitters
/ Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN) ; Tavernier, F (Leuven U.) ; Prinzie, J (Leuven U.)
Ongoing developments in the field of radiation-toleranthigh-speed transmitters (HSTs)aim at increasing thedata rates above 25 Gb/s while increasingtotal ionizing dose (TID)tolerance above 1 Grad. The use of half-ratearchitectures imposes tight constraints on clock signal quality, in particular itsduty-cycle. [...]
2024 - 7 p.
- Published in : JINST 19 (2024) C02030
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02030
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Test bench of a 100 Gbps radiation hardened link for future particle accelerators
/ Martina, F (CERN) ; Baron, S (CERN) ; Moreira, P (CERN) ; Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Klekotko, A (CERN ; Leuven U.) ; Kulis, S (CERN)
Pioneering physics experiments require increasingly faster data transfers and high-throughput electronics, which drives the research towards a new class of serialisers and optical links. In this framework, the DART28, a 100 Gbps radiation tolerant serialiser and driver, has been designed in 28 nm CMOS technology, submitted in April and delivered in August 2023. [...]
2024 - 7 p.
- Published in : JINST 19 (2024) C02072
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C02072
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Dual use driver for high speed links transmitters in the future high energy physics experiments
/ Baszczyk, M (CERN) ; Biereigel, S (CERN) ; Klekotko, A (CERN ; Leuven U.) ; Kulis, S (CERN) ; Martina, F (CERN) ; Moreira, P (CERN)
The paper presents the Dual Use Driver (DUDE) for highspeed links, a circuit designed for the Demonstrator ASIC for Radiation-Tolerant Transmitter in 28 nm CMOS (DART28) developed under the EP-R&D; programme on technologies for future high energyphysics experiments. The driver operates at 25.6 Gbps and it allows driving both 100 Ωtransmission lines and optical Ring Modulators (RMs) integrated in a photonics integrated circuit(PIC). [...]
2024 - 7 p.
- Published in : JINST 19 (2024) C03013
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2023 (TWEPP 2023), Geremeas, Sardinia, Italy, 1 - 6 Oct 2023, pp.C03013
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Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS
/ Klekotko, A (Leuven U. ; CERN) ; Baszczyk, M (CERN) ; Biereigel, S (Leuven U. ; CERN) ; Kulis, S (CERN) ; Moreira, P (CERN) ; Prinzie, J (Leuven U.) ; Tavernier, F (Leuven U.)
True Single-Phase-Clock (TSPC) dynamic logic is widely used in high-speed circuits such as high-speed SERDES (Serializer/Deserializer) and frequency dividers. TSPC flip-flops (FF) are known for their high operational speed and low power consumption, compared to static FFs. [...]
2023 - 8 p.
- Published in : JINST 18 (2023) C02068
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C02068
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Radiation-tolerant all-digital clock generators for HEP applications
/ Biereigel, S (CERN ; Geel, Cathol. High Sch. Kempen ; Brandenburg Tech. U.) ; Kulis, S (CERN) ; Mendes, E (CERN) ; Hazell, P (CERN) ; Moreira, P (CERN) ; Prinzie, J (Geel, Cathol. High Sch. Kempen)
The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. [...]
2023 - 8 p.
- Published in : JINST 18 (2023) C01060
Fulltext: PDF;
In : Topical Workshop on Electronics for Particle Physics 2022 (TWEPP 2022), Bergen, Norway, 19 - 23 Sep 2022, pp.C01060
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