| ATLAS Note | |
| Report number | ATL-ITK-PROC-2024-006 |
| Title | Analysis of MOS capacitor with p layer with TCAD simulation |
| Author(s) |
Unno, Yoshinobu (High Energy Accelerator Research Organization (JP)) (+) ; Dandoy, Jeff (Carleton University (CA)) (+) ; Fadeyev, Vitaliy (University of California,Santa Cruz (US)) (+) ; Fleta Corral, Celeste (Consejo Superior de Investigaciones Cientificas (CSIC) (ES)) (+) ; Jessiman, Callan (Carleton University (CA)) (+) ; Keller, John Stakely (Carleton University (CA)) (+) ; Klein, Christoph Thomas (Carleton University (CA)) (+) ; Koffas, Thomas (Carleton University (CA)) (+) ; Staats, Ezekiel (Carleton University (CA)) (+) ; Ullan, Miguel (Consejo Superior de Investigaciones Cientificas (CSIC) (ES)) (+) ; Bach Marques, Eric (Consejo Superior de Investigaciones Cientificas (CSIC) (ES)) (+) |
| Corporate Author(s) | The ATLAS collaboration |
| Publication | 2024 |
| Imprint | 13 Feb 2024 |
| Number of pages | 5 |
| In: | 13th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Vancouver, Canada, 3 - 8 Dec 2023 |
| Subject category | Particle Physics - Experiment |
| Accelerator/Facility, Experiment | CERN LHC ; ATLAS |
| Free keywords | n-in-p ; p-type ; strip ; silicon ; radiation tolerant ; HL-LHC ; TCAD ; simulation |
| Abstract | The ATLAS18 strip sensors of the ATLAS inner tracker upgrade (ITk) are in production since 2021. Along with the large-format n$^+$-in-p strip sensor in the center of 6-inch wafer, test structures are laid out in the open space for monitoring the performance of the strip sensor and its fabrication process. One of the structures is a 1.2$\times$1.0 cm$^2$ test chip that includes representative structures of the strips, and Metal-Oxide-Silicon (MOS) capacitors. In addition to the standard MOS capacitor, a MOS capacitor is designed with a p-implantation in the surface of silicon, representative of the p-stop doping for isolating the n$^+$ strips, the MOS-p capacitor. The capacitance measurement of the standard MOS capacitor as a function of bias voltage (C-V) shows characteristic behavior in the accumulation, depletion, and inversion regimes, from which one can deduce the amount of the interface charge. The MOS-p capacitor shows the C-V behavior modulated by the properties of the p-layer. With over 50% of the full production complement delivered, we have observed consistent characteristics in the MOS-p capacitors. Rarely and currently only in three batches, we have observed abnormalities which have implied lower density of p-implantation in the p-layer. To study the cause, we have simulated the MOS-p capacitor with a TCAD software, which successfully reproduces the normal behavior, with the p-density and the interface charge within the expected ranges, including a feature caused by a geometrical offset of the areas of the metal and the p-implantation. By contrast, overall shapes of the abnormal cases are only reproduced when introducing 1/10 of p-density, larger interface charge, charge traps in the p-layer, and/or n-type surface contamination. A smaller but distinctive feature in the C-V behavior might also be caused by non-uniform distribution of these or other components. These simulations help to take final acceptance decisions for the batches in production. |
Registre creat el 2024-02-13, darrera modificació el 2024-02-13
- Afegeix-lo al cistell personal
- Anomena i desa BibTeX, MARC, MARCXML, DC, EndNote, NLM, Authors Contributions, RefWorks