CERN Accelerating science

Article
Title	A Compact Front-End Circuit for a Monolithic Sensor in a 65-nm CMOS Imaging Technology
Author(s)	Piro, F (CERN ; Ecole Polytechnique, Lausanne) ; Rinella, G Aglieri (CERN) ; Andronic, A (U. Munster) ; Antonelli, M (INFN, Trieste) ; Aresti, M (Cagliari U. ; INFN, Cagliari) ; Baccomi, R (INFN, Trieste) ; Becht, P (Heidelberg U.) ; Beolè, S (Turin U. ; INFN, Turin) ; Braach, J (CERN) ; Buckland, M D (INFN, Trieste ; Trieste U.) ; Buschmann, E (CERN) ; Camerini, P (INFN, Trieste ; Trieste U.) ; Carnesecchi, F (CERN) ; Cecconi, L (CERN) ; Charbon, E (Ecole Polytechnique, Lausanne) ; Contin, G (INFN, Trieste ; Trieste U.) ; Dannheim, D (CERN) ; de Melo, J (CERN) ; Deng, W (CERN) ; di Mauro, A (CERN) ; Dimitrova Vassilev, M (Stanford U.) ; Emiliani, S (CERN) ; Hasenbichler, J (CERN) ; Hillemanns, H (CERN) ; Hong, G H (CERN) ; Isakov, A (Rez, Nucl. Phys. Inst.) ; Junique, A (CERN) ; Kluge, A (CERN) ; Kotliarov, A (Rez, Nucl. Phys. Inst.) ; Křížek, F (Rez, Nucl. Phys. Inst.) ; Kugathasan, T (CERN ; Geneva U.) ; Lautner, L (CERN) ; Lemoine, C (CERN) ; Mager, M (CERN) ; Marras, D (Cagliari U. ; INFN, Cagliari) ; Martinengo, P (CERN) ; Masciocchi, S (Heidelberg U.) ; Menzel, M W (Heidelberg U.) ; Munker, M (CERN) ; Rachevski, A (INFN, Trieste) ; Rebane, K (CERN) ; Reidt, F (CERN) ; Russo, R (Nikhef, Amsterdam) ; Sanna, I (CERN) ; Sarritzu, V (Cagliari U. ; INFN, Cagliari) ; Senyukov, S (CNRS, France) ; Snoeys, W (CERN) ; Sonneveld, J (Nikhef, Amsterdam) ; Šuljić, M (CERN) ; Svihra, P (CERN) ; Tiltmann, N (U. Munster) ; Usai, G (Cagliari U. ; INFN, Cagliari) ; van Beelen, J B (CERN) ; Vernieri, C (Stanford U.) ; Villani, A (INFN, Trieste ; Trieste U.)
Publication	2023
Number of pages	10
In:	IEEE Trans. Nucl. Sci. 70 (2023) 2191-2200
DOI	10.1109/tns.2023.3299333
Subject category	Detectors and Experimental Techniques
Abstract	This article presents the design of a front-end circuit for monolithic active pixel sensors (MAPSs). The circuit operates with a sensor featuring a small, low-capacitance (< 2 fF) collection electrode and is integrated into the DPTS chip, a proof-of-principle prototype of 1.5×1.5 mm including a matrix of 32×32 pixels with a pitch of 15μm . The chip is implemented in the 65-nm imaging technology from the Tower Partners Semiconductor Company foundry and was developed in the framework of the EP-Research and Development Program at CERN to explore this technology for particle detection. The front-end circuit has an area of 42μm2 and can operate with power consumption as low as 12 nW. Measurements on the prototype relevant to the front end will be shown to support its design.
Copyright/License	publication: (License: CC-BY-4.0)

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