CERN Accelerating science

Article
Report number	arXiv:2110.12625 ; FERMILAB-CONF-21-633-PPD
Title	A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
Author(s)	Sun, H. (Southern Methodist U. ; Hua-Zhong Normal U.) ; Sun, Q. (Fermilab) ; Biereigel, S. (CERN ; Leuven U.) ; Francisco, R. (CERN) ; Gong, D. (Southern Methodist U.) ; Huang, G. (Hua-Zhong Normal U.) ; Huang, X. (Southern Methodist U.) ; Kulis, S. (CERN) ; Leroux, P. (Leuven U.) ; Liu, C. (Southern Methodist U.) ; Liu, T. (Southern Methodist U.) ; Moreira, P. (Southern Methodist U.) ; Prinzie, J. (Leuven U.) ; Wu, J. (Fermilab) ; Ye, J. (Southern Methodist U.) ; Zhang, L. (Southern Methodist U. ; Hua-Zhong Normal U.) ; Zhang, W. (Southern Methodist U. ; Hua-Zhong Normal U.) ; Liu, T. (Fermilab)
Publication	2022-03-23
Imprint	2021-10-24
Number of pages	6
In:	TWEPP 2021 Topical Workshop on Electronics for Particle Physics, Online, Online, 20 - 24 Sep 2021, pp.C03038
DOI	10.1088/1748-0221/17/03/C03038 (publication)
Subject category	Particle Physics - Experiment ; Detectors and Experimental Techniques
Abstract	We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear energy transfer (LET) from 1.3 to 62.5 MeV*cm^2/mg.
Copyright/License	preprint: (License: arXiv nonexclusive-distrib 1.0) publication: © 2022-2024 IOP Publishing Ltd and Sissa Medialab

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