LATTICE QUANTUM CHROMODYNAMICS

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Preprint
Report number	hep-lat/0102011
Title	apeNEXT : A Multi-Tflops LQCD Computing Project
Related title	LATTICE QCD MULTITFLOPS LATTICE QUANTUM CHROMODYNAMICS QUANTUM CHROMODYNAMICS
Author(s)	Alfieri, R. (Parma U. ; INFN, Parma) ; Di Renzo, R. (Parma U. ; INFN, Parma) ; Onofri, E. (Parma U. ; INFN, Parma) ; Bartoloni, A. (Rome U. ; INFN, Rome) ; Battista, C. (Rome U. ; INFN, Rome) ; Cabibbo, N. (Rome U. ; INFN, Rome) ; Cosimi, M. (Rome U. ; INFN, Rome) ; Lonardo, A. (Rome U. ; INFN, Rome) ; Michelotti, A. (Rome U. ; INFN, Rome) ; Rapuano, F. (Rome U. ; INFN, Rome) ; Proietti, B. (Rome U. ; INFN, Rome) ; Rossetti, D. (Rome U. ; INFN, Rome) ; Sacco, G. (Rome U. ; INFN, Rome) ; Tassa, S. (Rome U. ; INFN, Rome) ; Torelli, M. (Rome U. ; INFN, Rome) ; Vicini, P. (Rome U. ; INFN, Rome) ; Boucaud, Philippe (Orsay, LPT) ; Pene, O. (Orsay, LPT) ; Errico, W. (INFN, Pisa) ; Magazzu, G. (INFN, Pisa) ; Sartori, L. (INFN, Pisa) ; Schifano, F. (INFN, Pisa) ; Tripiccione, R. (INFN, Pisa) ; De Riso, P. (Rome U., Tor Vergata ; INFN, Rome2) ; Petronzio, R. (Rome U., Tor Vergata ; INFN, Rome2) ; Destri, C. (Milan Bicocca U. ; INFN, Milan) ; Frezzotti, R. (Milan Bicocca U. ; INFN, Milan) ; Marchesini, G. (Milan Bicocca U. ; INFN, Milan) ; Gensch, U. (DESY, Zeuthen) ; Kretzschmann, A. (DESY, Zeuthen) ; Leich, H. (DESY, Zeuthen) ; Paschedag, N. (DESY, Zeuthen) ; Schwendicke, U. (DESY, Zeuthen) ; Simma, H. (DESY, Zeuthen) ; Sommer, R. (DESY, Zeuthen) ; Sulanke, K. (DESY, Zeuthen) ; Wegner, P. (DESY, Zeuthen) ; Pleiter, D. (DESY, Zeuthen) ; Jansen, K. (DESY, Zeuthen) ; Fucci, A. (CERN) ; Martin, B. (CERN) ; Pech, J. (CERN) ; Panizzi, E. (L'Aquila U. ; INFN, Rome) ; Petricola, A. (L'Aquila U. ; Gran Sasso)
Publication	2001
Imprint	25 Feb 2001
Number of pages	53
Note	53 pages, 10 figures
Subject category	Particle Physics - Lattice
Abstract	This paper is a slightly modified and reduced version of the proposal of the {\bf apeNEXT} project, which was submitted to DESY and INFN in spring 2000. .It presents the basic motivations and ideas of a next generation lattice QCD (LQCD) computing project, whose goal is the construction and operation of several large scale Multi-TFlops LQCD engines, providing an integrated peak performance of tens of TFlops, and a sustained (double precision) performance on key LQCD kernels of about 50% of peak speed.
Other source	Inspire
Submitted by	federico.rapuano@roma1.infn.it

$noimg: Local vs. remote memory access patterns: $\rho$ is the ratio of memory accesses to local memory over memory accesses to neighbour nodes in a simple implementation of the solver for the Dirac operator. $\rho$ is estimated as a function of the linear size of the sub-lattice mapped onto {\em each} processor.: Local vs remote memory accesses: this table is the same as the previous one, except that $\rho$ is estimated taking into account the trick, described in the text, that reduces remote accesses. The last two entries refer to non-square sub-lattices that might be used when simulating a lattice of spatial size $48^3$ on large machines with $16 \times 8 \times 8$ or $16 \times 12 \times 12$ nodes.: Data structures used in LQCD and corresponding memory requirements (in words and fermion equivalent storage) per lattice point. Greek indices run from $1$ to $4$ and Latin indices from $1$ to $3$. The first three entries are general complex matrices, while the Pauli term is hermitian: $(\sigma \cdot F)_{ab}^{\alpha\beta} = [(\sigma \cdot F)_{ba}^{\beta\alpha}]^*$.: Total memory requirements for the case studies discussed in the text. The line labeled {\em + disk} refers to the case in which two propagators only are kept in memory (all others being swapped onto disk or recomputed).: A short list of some large APEmille existing installations and of plans for the near future.: A summary of some key parameters for digital silicon technologies used in APEmille and proposed for {\bf apeNEXT}. All values are directly obtained from the relevant silicon foundries, except for the bit density of 1 Port or 2 Ports memory arrays in the UMC technology. The latter are based on conservatively applied scaling rules: A summary of several important figures for two options of dynamic RAM's. The second and third columns refer to presently available DDR and RAMBUS devices. The fourth and fifth columns refer to the expected evolution of these devices in the next two years.: Basic features of two possible memory systems for {\bf apeNEXT} based on DDRAM memory technology. Power consumption is estimated by rescaling data available for present generation systems: Basic figures for several link technologies. All figures refer to full duplex links. An 8 bit into 10 bit encoding has been assumed for the LVDS case.: Features of the AMD Athlon processor relevant for LQCD simulations. Sustained performance is estimated under the assumptions discussed in the text.$ $Power consumption (W) of the AMD Athlon processor as a function of the clock frequency (MHz) \cite{AMD}.$ $The Crusoe architecture (adapted from \cite{crusoe}.$ Show more plots

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